struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 2;
tdma_case = 100;
}
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 2;
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 1;
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_coex_rfe *coex_rfe = &coex->rfe;
u8 table_case = 0xff, tdma_case = 0xff;
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (coex_rfe->ant_switch_with_bt &&
coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
if (efuse->share_ant &&
}
}
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
u8 table_case, tdma_case;
u32 slot_type = 0;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (coex_stat->wl_linkscan_proc || coex_stat->wl_hi_pri_task1 ||
coex_stat->wl_hi_pri_task2)
wl_hi_pri = true;
rtw_dbg(rtwdev, RTW_DBG_COEX, "coex: wifi hi(%d), bt page(%d)\n",
wl_hi_pri, coex_stat->bt_page);
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case | slot_type);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
if (coex_stat->bt_multi_link) {
}
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
u8 table_case, tdma_case;
u32 wl_bw;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
wl_bw = rtwdev->hal.current_band_width;
if (efuse->share_ant) {
}
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
u8 table_case, tdma_case;
u32 slot_type = 0;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
slot_type = TDMA_4SLOT;
tdma_case = 113;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case | slot_type);
}
u8 table_case, tdma_case;
bool ap_enable = false;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) { /* Shared-Ant */
if (ap_enable) {
table_case = 2;
}
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
tdma_case = 119;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
u8 table_case, tdma_case;
u32 slot_type = 0;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
slot_type = TDMA_4SLOT;
tdma_case = 113;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case | slot_type);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
if (coex_stat->wl_gl_busy &&
tdma_case = 120;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 9;
tdma_case = 119;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 10;
tdma_case = 120;
}
- rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_5G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
rtw_coex_write_scbd(rtwdev, COEX_SCBD_FIX2M, false);
if (efuse->share_ant) {
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_5G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 2;
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
if (coex->under_5g)
return;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 28;
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}
u8 table_case, tdma_case;
u32 slot_type = 0;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
if (coex_stat->bt_a2dp_exist) {
}
}
- rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case | slot_type);
}
struct rtw_chip_info *chip = rtwdev->chip;
u8 table_case, tdma_case;
+ rtw_coex_set_ant_path(rtwdev, false, COEX_SET_ANT_2G);
+ rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+
if (efuse->share_ant) {
/* Shared-Ant */
table_case = 1;
tdma_case = 100;
}
- rtw_coex_set_ant_path(rtwdev, true, COEX_SET_ANT_2G);
- rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
rtw_coex_table(rtwdev, table_case);
rtw_coex_tdma(rtwdev, false, tdma_case);
}