dmaengine: xilinx_dma: program hardware supported buffer length

AXI-DMA IP supports configurable (c_sg_length_width) buffer length
register width, hence read buffer length (xlnx,sg-length-width) DT
property and ensure that driver doesn't program buffer length
exceeding the supported limit. For VDMA and CDMA there is no change.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com> [rebase, reword]
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 93435f7..d59af2b 100644 (file)
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -161,7 +161,9 @@
 #define XILINX_DMA_REG_BTT             0x28
 
 /* AXI DMA Specific Masks/Bit fields */
-#define XILINX_DMA_MAX_TRANS_LEN       GENMASK(22, 0)
+#define XILINX_DMA_MAX_TRANS_LEN_MIN   8
+#define XILINX_DMA_MAX_TRANS_LEN_MAX   23
+#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX        26
 #define XILINX_DMA_CR_COALESCE_MAX     GENMASK(23, 16)
 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK        BIT(4)
 #define XILINX_DMA_CR_COALESCE_SHIFT   16
@@ -2626,7 +2628,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
        struct xilinx_dma_device *xdev;
        struct device_node *child, *np = pdev->dev.of_node;
        struct resource *io;
-       u32 num_frames, addr_width;
+       u32 num_frames, addr_width, len_width;
        int i, err;
 
        /* Allocate and initialize the DMA engine structure */
@@ -2658,10 +2660,24 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 
        /* Retrieve the DMA engine properties from the device tree */
        xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
-       xdev->max_buffer_len = XILINX_DMA_MAX_TRANS_LEN;
+       xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
 
-       if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
+       if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
                xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
+               if (!of_property_read_u32(node, "xlnx,sg-length-width",
+                                         &len_width)) {
+                       if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN ||
+                           len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) {
+                               dev_warn(xdev->dev,
+                                        "invalid xlnx,sg-length-width property value. Using default width\n");
+                       } else {
+                               if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX)
+                                       dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n");
+                               xdev->max_buffer_len =
+                                       GENMASK(len_width - 1, 0);
+                       }
+               }
+       }
 
        if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
                err = of_property_read_u32(node, "xlnx,num-fstores",