[PATCH 6] intel_soc_clv: Adding PM support for CLV

BZ: 26897

This patch enables PM support for cloverview platform.

Change-Id: I1c42e8a00df1ea11e6410011902bfd371bf51098
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Nivedha Krishnakumar <nivedha.krishnakumar@intel.com>
Signed-off-by: Ramachandra Sudarshan N <sudarshan.n.ramachandra@intel.com>
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Dyut K Sil <dyut.k.sil@intel.com>
Reviewed-on: http://android.intel.com:8080/40188
Reviewed-by: Mansoor, Illyas <illyas.mansoor@intel.com>
Reviewed-by: Gross, Mark <mark.gross@intel.com>
Tested-by: Martin, LoicX <loicx.martin@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1da4426..a73cff9 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1962,6 +1962,13 @@ config INTEL_ATOM_MDFLD_POWER
        Power management driver for medfield Platform.
        If you don't know what to do here, say N.
 
+config INTEL_ATOM_CLV_POWER
+       bool "Power Management driver for Intel cloverview platform"
+       depends on PCI && CPU_IDLE && PM_RUNTIME && PM_SLEEP && X86_MDFLD
+       select ATOM_SOC_POWER
+       ---help---
+       Power management driver for cloverview Platform.
+       If you don't know what to do here, say N.
 endmenu
 
 menu "Bus options (PCI etc.)"

diff --git a/arch/x86/platform/intel-mid/Makefile b/arch/x86/platform/intel-mid/Makefile
index bd98bab..f69588a 100644 (file)
--- a/arch/x86/platform/intel-mid/Makefile
+++ b/arch/x86/platform/intel-mid/Makefile
@@ -1,6 +1,7 @@
 CFLAGS_intel_soc_pm_debug.o            := -Werror
 CFLAGS_intel_soc_pmu.o                 := -Werror
 CFLAGS_intel_soc_mdfld.o               := -Werror
+CFLAGS_intel_soc_clv.o                 := -Werror
 
 # platform configuration for board devices
 obj-y                                  += device_libs/
@@ -21,6 +22,7 @@ obj-$(CONFIG_X86_MRFLD)                       += mrfl.o
 
 obj-$(CONFIG_ATOM_SOC_POWER)           += intel_soc_pm_debug.o intel_soc_pmu.o
 obj-$(CONFIG_INTEL_ATOM_MDFLD_POWER)   += intel_soc_mdfld.o
+obj-$(CONFIG_INTEL_ATOM_CLV_POWER)     += intel_soc_clv.o
 
 # BOARD files
 obj-$(CONFIG_BOARD_MFLD_BLACKBAY)      += board-blackbay.o

diff --git a/arch/x86/platform/intel-mid/intel_soc_clv.c b/arch/x86/platform/intel-mid/intel_soc_clv.c
new file mode 100644 (file)
index 0000000..73085d6
--- /dev/null
+++ b/arch/x86/platform/intel-mid/intel_soc_clv.c
@@ -0,0 +1,106 @@
+/*
+ * intel_soc_clv.c - This driver provides utility api's for
+ * Cloverview platform
+ * Copyright (c) 2012, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include "intel_soc_pmu.h"
+
+/**
+ *      platform_set_pmu_ops - Set the global pmu method table.
+ *      @ops:   Pointer to ops structure.
+ */
+void platform_set_pmu_ops(void)
+{
+       pmu_ops = &clv_pmu_ops;
+}
+
+static int clv_pmu_init(void)
+{
+       return 0;
+}
+
+static u32 clv_pmu_enter(int s0ix_state)
+{
+       u32 s0ix_value = 0;
+       int num_retry = PMU_MISC_SET_TIMEOUT;
+
+       if (unlikely(need_resched()))
+               return s0ix_value;
+
+       s0ix_value = get_s0ix_val_set_pm_ssc(s0ix_state);
+
+       /* issue a command to SCU */
+       writel(s0ix_value, &mid_pmu_cxt->pmu_reg->pm_cmd);
+
+       do {
+               if (readl(&mid_pmu_cxt->pmu_reg->pm_msic))
+                       break;
+               udelay(1);
+       } while (--num_retry);
+
+       if (!num_retry && !readl(&mid_pmu_cxt->pmu_reg->pm_msic))
+               WARN(1, "%s: pm_msic not set.\n", __func__);
+
+       mid_pmu_cxt->s0ix_entered = s0ix_state;
+
+       return s0ix_value;
+}
+
+static void clv_pmu_remove(void)
+{
+       /* Place holder */
+}
+
+static void clv_pmu_wakeup(void)
+{
+
+       /* Wakeup allother CPU's */
+       if (mid_pmu_cxt->s0ix_entered == MID_S0I3_STATE)
+               apic->send_IPI_allbutself(RESCHEDULE_VECTOR);
+}
+
+static pci_power_t clv_pmu_choose_state(int device_lss)
+{
+       pci_power_t state;
+
+       switch (device_lss) {
+       case PMU_SECURITY_LSS_04:
+               state = PCI_D2;
+               break;
+
+       case PMU_USB_OTG_LSS_06:
+       case PMU_USB_HSIC_LSS_07:
+       case PMU_UART2_LSS_41:
+               state = PCI_D1;
+               break;
+
+       default:
+               state = PCI_D3hot;
+               break;
+       }
+
+       return state;
+}
+
+struct platform_pmu_ops clv_pmu_ops = {
+       .init           = clv_pmu_init,
+       .enter           = clv_pmu_enter,
+       .wakeup          = clv_pmu_wakeup,
+       .remove         = clv_pmu_remove,
+       .pci_choose_state = clv_pmu_choose_state,
+};

diff --git a/arch/x86/platform/intel-mid/intel_soc_clv.h b/arch/x86/platform/intel-mid/intel_soc_clv.h
new file mode 100644 (file)
index 0000000..c9cde16
--- /dev/null
+++ b/arch/x86/platform/intel-mid/intel_soc_clv.h
@@ -0,0 +1,333 @@
+/*
+ * intel_soc_clv.h
+ * Copyright (c) 2012, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifdef CONFIG_INTEL_ATOM_CLV_POWER
+
+#define   PM_SUPPORT                           0x21
+
+#define ISP_POS                        7
+#define ISP_SUB_CLASS          0x80
+#define PMU_MISC_SET_TIMEOUT   15000
+
+#define GFX_LSS_INDEX                  1
+#define PMU_SDIO0_LSS_00               0
+#define PMU_EMMC0_LSS_01               1
+#define PMU_AONT_LSS_02                        2
+#define PMU_HSI_LSS_03                 3
+#define PMU_SECURITY_LSS_04            4
+#define PMU_EMMC1_LSS_05               5
+#define PMU_USB_OTG_LSS_06             6
+#define PMU_USB_HSIC_LSS_07            7
+#define PMU_AUDIO_ENGINE_LSS_08                8
+#define PMU_AUDIO_DMA_LSS_09           9
+#define PMU_SRAM_LSS_10                        10
+#define PMU_SRAM_LSS_11                        11
+#define PMU_SRAM_LSS_12                        12
+#define PMU_SRAM_LSS_13                        13
+#define PMU_SDIO2_LSS_14               14
+#define PMU_PTI_DAFCA_LSS_15           15
+#define PMU_SC_DMA_LSS_16              16
+#define PMU_SPIO_LSS_17                        17
+#define PMU_SPI1_LSS_18                        18
+#define PMU_SPI2_LSS_19                        19
+#define PMU_I2C0_LSS_20                        20
+#define PMU_I2C1_LSS_21                        21
+#define PMU_MAIN_FABRIC_LSS_22         22
+#define PMU_SEC_FABRIC_LSS_23          23
+#define PMU_SC_FABRIC_LSS_24           24
+#define PMU_AUDIO_RAM_LSS_25           25
+#define PMU_SCU_ROM_LSS_26             26
+#define PMU_I2C2_LSS_27                        27
+#define PMU_SSC_LSS_28                 28
+#define PMU_SECURITY_LSS_29            29
+#define PMU_SDIO1_LSS_30               30
+#define PMU_SCU_RAM0_LSS_31            31
+#define PMU_SCU_RAM1_LSS_32            32
+#define PMU_I2C3_LSS_33                        33
+#define PMU_I2C4_LSS_34                        34
+#define PMU_I2C5_LSS_35                        35
+#define PMU_SPI3_LSS_36                        36
+#define PMU_GPIO1_LSS_37               37
+#define PMU_PWR_BUTTON_LSS_38          38
+#define PMU_GPIO0_LSS_39               39
+#define PMU_KEYBRD_LSS_40              40
+#define PMU_UART2_LSS_41               41
+#define PMU_ADC_LSS_42                 42
+#define PMU_CHARGER_LSS_43             43
+#define PMU_SEC_TAPC_LSS_44            44
+#define PMU_RTC_LSS_45                 45
+#define PMU_GPI_LSS_46                 46
+#define PMU_HDMI_VREG_LSS_47           47
+#define PMU_RESERVED_LSS_48            48
+#define PMU_AUDIO_SLIM1_LSS_49         49
+#define PMU_RESET_LSS_50               50
+#define PMU_AUDIO_SSP0_LSS_51          51
+#define PMU_AUDIO_SSP1_LSS_52          52
+#define PMU_IOSF_OCP_BRG_LSS_53                53
+#define PMU_GP_DMA_LSS_54              54
+#define PMU_SVID_LSS_55                        55
+#define PMU_SOC_FUSE_LSS_56            56
+#define PMU_RSVD3_LSS_57               57
+#define PMU_RSVD4_LSS_58               58
+#define PMU_RSVD5_LSS_59               59
+#define PMU_RSVD6_LSS_60               60
+#define PMU_RSVD7_LSS_61               61
+#define PMU_RSVD8_LSS_62               62
+#define PMU_RSVD9_LSS_63               63
+
+#define S0IX_TARGET_SSS0_MASK ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I3_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I3_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_DMA_LSS_09) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define S0IX_TARGET_SSS1_MASK ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+#define S0IX_TARGET_SSS2_MASK ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I3_MASK, PMU_UART2_LSS_41-32))
+
+#define S0IX_TARGET_SSS3_MASK ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48))
+
+#define S0IX_TARGET_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_DMA_LSS_09) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define S0IX_TARGET_SSS1 ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+
+#define S0IX_TARGET_SSS2 ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
+
+#define S0IX_TARGET_SSS3 ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48))
+
+#define LPMP3_TARGET_SSS0_MASK ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I3_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I3_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define LPMP3_TARGET_SSS1_MASK ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+
+#define LPMP3_TARGET_SSS2_MASK ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I3_MASK, PMU_UART2_LSS_41-32))
+
+#define LPMP3_TARGET_SSS3_MASK ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48))
+
+#define LPMP3_TARGET_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I0_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define LPMP3_TARGET_SSS1 ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+
+#define LPMP3_TARGET_SSS2 ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
+
+#define LPMP3_TARGET_SSS3 ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48))
+
+#define IGNORE_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_USB_HSIC_LSS_07) | \
+       SSMSK(D0I3_MASK, PMU_SRAM_LSS_10) | \
+       SSMSK(D0I3_MASK, PMU_SRAM_LSS_11) | \
+       SSMSK(D0I3_MASK, PMU_SRAM_LSS_12) | \
+       SSMSK(D0I3_MASK, PMU_SRAM_LSS_13) | \
+       SSMSK(D0I3_MASK, PMU_PTI_DAFCA_LSS_15))
+
+#define IGNORE_SSS1 ( \
+       SSMSK(D0I3_MASK, PMU_SC_DMA_LSS_16-16) | \
+       SSMSK(D0I3_MASK, PMU_SPIO_LSS_17-16) | \
+       SSMSK(D0I3_MASK, PMU_MAIN_FABRIC_LSS_22-16) | \
+       SSMSK(D0I3_MASK, PMU_SEC_FABRIC_LSS_23-16) | \
+       SSMSK(D0I3_MASK, PMU_SC_FABRIC_LSS_24-16) | \
+       SSMSK(D0I3_MASK, PMU_SCU_ROM_LSS_26-16) | \
+       SSMSK(D0I3_MASK, PMU_SSC_LSS_28-16) | \
+       SSMSK(D0I3_MASK, PMU_SECURITY_LSS_29-16) | \
+       SSMSK(D0I3_MASK, PMU_SCU_RAM0_LSS_31-16))
+
+#define IGNORE_SSS2 ( \
+       SSMSK(D0I3_MASK, PMU_SCU_RAM1_LSS_32-32) | \
+       SSMSK(D0I3_MASK, PMU_GPIO1_LSS_37-32) | \
+       SSMSK(D0I3_MASK, PMU_PWR_BUTTON_LSS_38-32) | \
+       SSMSK(D0I3_MASK, PMU_GPIO0_LSS_39-32) | \
+       SSMSK(D0I3_MASK, PMU_ADC_LSS_42-32) | \
+       SSMSK(D0I3_MASK, PMU_CHARGER_LSS_43-32) | \
+       SSMSK(D0I3_MASK, PMU_SEC_TAPC_LSS_44-32) | \
+       SSMSK(D0I3_MASK, PMU_RTC_LSS_45-32) | \
+       SSMSK(D0I3_MASK, PMU_GPI_LSS_46-32) | \
+       SSMSK(D0I3_MASK, PMU_HDMI_VREG_LSS_47-32))
+
+#define IGNORE_SSS3 ( \
+       SSMSK(D0I3_MASK, PMU_IOSF_OCP_BRG_LSS_53-48) | \
+       SSMSK(D0I3_MASK, PMU_SVID_LSS_55-48) | \
+       SSMSK(D0I3_MASK, PMU_SOC_FUSE_LSS_56-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD3_LSS_57-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD4_LSS_58-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD5_LSS_59-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD6_LSS_60-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD7_LSS_61-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD8_LSS_62-48) | \
+       SSMSK(D0I3_MASK, PMU_RSVD9_LSS_63-48))
+
+#define IGNORE_S3_WKC0 SSWKC(PMU_AONT_LSS_02)
+#define IGNORE_S3_WKC1 SSWKC(PMU_ADC_LSS_42-32)
+
+/* FIXME:: CVT Platform gives SRAM Error if SRAM is put in D0i3 */
+#define S0I3_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_AONT_LSS_02) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I1_MASK, PMU_USB_HSIC_LSS_07) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_ENGINE_LSS_08) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_DMA_LSS_09) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define S0I3_SSS1 ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_SPI2_LSS_19-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_RAM_LSS_25-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+
+#define S0I3_SSS2 ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I3_MASK, PMU_GPIO1_LSS_37-32) | \
+       SSMSK(D0I3_MASK, PMU_PWR_BUTTON_LSS_38-32) | \
+       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
+       SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
+
+#define S0I3_SSS3 ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SLIM1_LSS_49-48) | \
+       SSMSK(D0I3_MASK, PMU_RESET_LSS_50-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48) | \
+       SSMSK(D0I3_MASK, PMU_GP_DMA_LSS_54-48))
+
+#define S0I1_SSS0 S0I3_SSS0
+#define S0I1_SSS1 S0I3_SSS1
+#define S0I1_SSS2 S0I3_SSS2
+#define S0I1_SSS3 S0I3_SSS3
+
+#define LPMP3_SSS0 ( \
+       SSMSK(D0I3_MASK, PMU_SDIO0_LSS_00) | \
+       SSMSK(D0I3_MASK, PMU_EMMC0_LSS_01) | \
+       SSMSK(D0I3_MASK, PMU_AONT_LSS_02) | \
+       SSMSK(D0I3_MASK, PMU_HSI_LSS_03) | \
+       SSMSK(D0I2_MASK, PMU_SECURITY_LSS_04) | \
+       SSMSK(D0I3_MASK, PMU_EMMC1_LSS_05) | \
+       SSMSK(D0I1_MASK, PMU_USB_OTG_LSS_06) | \
+       SSMSK(D0I1_MASK, PMU_USB_HSIC_LSS_07) | \
+       SSMSK(D0I3_MASK, PMU_SDIO2_LSS_14))
+
+#define LPMP3_SSS1 ( \
+       SSMSK(D0I3_MASK, PMU_SPI1_LSS_18-16) | \
+       SSMSK(D0I3_MASK, PMU_SPI2_LSS_19-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C0_LSS_20-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C1_LSS_21-16) | \
+       SSMSK(D0I3_MASK, PMU_I2C2_LSS_27-16) | \
+       SSMSK(D0I3_MASK, PMU_SDIO1_LSS_30-16))
+
+#define LPMP3_SSS2 ( \
+       SSMSK(D0I3_MASK, PMU_I2C3_LSS_33-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C4_LSS_34-32) | \
+       SSMSK(D0I3_MASK, PMU_I2C5_LSS_35-32) | \
+       SSMSK(D0I3_MASK, PMU_SPI3_LSS_36-32) | \
+       SSMSK(D0I3_MASK, PMU_GPIO1_LSS_37-32) | \
+       SSMSK(D0I3_MASK, PMU_PWR_BUTTON_LSS_38-32) | \
+       SSMSK(D0I3_MASK, PMU_KEYBRD_LSS_40-32) | \
+       SSMSK(D0I1_MASK, PMU_UART2_LSS_41-32))
+
+#define LPMP3_SSS3 ( \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SLIM1_LSS_49-48) | \
+       SSMSK(D0I3_MASK, PMU_RESET_LSS_50-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP0_LSS_51-48) | \
+       SSMSK(D0I3_MASK, PMU_AUDIO_SSP1_LSS_52-48) | \
+       SSMSK(D0I3_MASK, PMU_GP_DMA_LSS_54-48))
+#endif

diff --git a/arch/x86/platform/intel-mid/intel_soc_pmu.c b/arch/x86/platform/intel-mid/intel_soc_pmu.c
index 9d73b38..bac4313 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_pmu.c
+++ b/arch/x86/platform/intel-mid/intel_soc_pmu.c
@@ -79,6 +79,7 @@ static int pci_to_platform_state(pci_power_t pci_state)
 /* PCI Device Id structure */
 static DEFINE_PCI_DEVICE_TABLE(mid_pm_ids) = {
        {PCI_VDEVICE(INTEL, MID_PMU_MFLD_DRV_DEV_ID), 0},
+       {PCI_VDEVICE(INTEL, MID_PMU_CLV_DRV_DEV_ID), 0},
        {}
 };
 

diff --git a/arch/x86/platform/intel-mid/intel_soc_pmu.h b/arch/x86/platform/intel-mid/intel_soc_pmu.h
index d376546..5904c26 100644 (file)
--- a/arch/x86/platform/intel-mid/intel_soc_pmu.h
+++ b/arch/x86/platform/intel-mid/intel_soc_pmu.h
@@ -40,6 +40,7 @@
 #include <asm/intel_scu_ipc.h>
 #include <linux/intel_mid_pm.h>
 #include "intel_soc_mdfld.h"
+#include "intel_soc_clv.h"
 
 #define MID_PMU_MFLD_DRV_DEV_ID                 0x0828
 #define MID_PMU_CLV_DRV_DEV_ID                 0x08EC