riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes

Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 46c4685..196dc14 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/power/starfive,jh7110-pmu.h>
 #include <dt-bindings/reset/starfive,jh7110-crg.h>
 
 / {
@@ -374,6 +375,25 @@
                        status = "disabled";
                };
 
+               stgcrg: clock-controller@10230000 {
+                       compatible = "starfive,jh7110-stgcrg";
+                       reg = <0x0 0x10230000 0x0 0x10000>;
+                       clocks = <&osc>,
+                                <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
+                                <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+                                <&syscrg JH7110_SYSCLK_USB_125M>,
+                                <&syscrg JH7110_SYSCLK_CPU_BUS>,
+                                <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
+                                <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
+                                <&syscrg JH7110_SYSCLK_APB_BUS>;
+                       clock-names = "osc", "hifi4_core",
+                                     "stg_axiahb", "usb_125m",
+                                     "cpu_bus", "hifi4_axi",
+                                     "nocstg_bus", "apb_bus";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
                stg_syscon: syscon@10240000 {
                        compatible = "starfive,jh7110-stg-syscon", "syscon";
                        reg = <0x0 0x10240000 0x0 0x1000>;
@@ -539,5 +559,40 @@
                        interrupts = <111>;
                        #power-domain-cells = <1>;
                };
+
+               ispcrg: clock-controller@19810000 {
+                       compatible = "starfive,jh7110-ispcrg";
+                       reg = <0x0 0x19810000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
+                                <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
+                                <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
+                                <&dvp_clk>;
+                       clock-names = "isp_top_core", "isp_top_axi",
+                                     "noc_bus_isp_axi", "dvp_clk";
+                       resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
+                                <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
+                                <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       power-domains = <&pwrc JH7110_PD_ISP>;
+               };
+
+               voutcrg: clock-controller@295c0000 {
+                       compatible = "starfive,jh7110-voutcrg";
+                       reg = <0x0 0x295c0000 0x0 0x10000>;
+                       clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+                                <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+                                <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+                                <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+                                <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+                                <&hdmitx0_pixelclk>;
+                       clock-names = "vout_src", "vout_top_ahb",
+                                     "vout_top_axi", "vout_top_hdmitx0_mclk",
+                                     "i2stx0_bclk", "hdmitx0_pixelclk";
+                       resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       power-domains = <&pwrc JH7110_PD_VOUT>;
+               };
        };
 };