drm/i915/dg2: Add Wa_1509727124

Bspec: 46052
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220801213839.8549-1-harish.chegondi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 60d6eb5..b3b49f6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1078,6 +1078,7 @@
 
 #define GEN10_SAMPLER_MODE                     _MMIO(0xe18c)
 #define   ENABLE_SMALLPL                       REG_BIT(15)
+#define   SC_DISABLE_POWER_OPTIMIZATION_EBB    REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG    REG_BIT(5)
 
 #define GEN9_HALF_SLICE_CHICKEN7               _MMIO(0xe194)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e8111fc..59cf28b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2119,6 +2119,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
        }
 
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+           IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+               /* Wa_1509727124:dg2 */
+               wa_masked_en(wal, GEN10_SAMPLER_MODE,
+                            SC_DISABLE_POWER_OPTIMIZATION_EBB);
+       }
+
        if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
            IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
                /* Wa_14012419201:dg2 */