drm/amdgpu/mes: add status fence memory definitions
authorLe Ma <le.ma@amd.com>
Fri, 20 Mar 2020 08:35:50 +0000 (16:35 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:11 +0000 (01:59 -0400)
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c

index 4da9d8f50578fa8b48f8a78ac3f957fa57298c84..7334982ea70276aefc43861c5e42549055c284b6 100644 (file)
@@ -82,6 +82,9 @@ struct amdgpu_mes {
        uint32_t                        sch_ctx_offs;
        uint64_t                        sch_ctx_gpu_addr;
        uint64_t                        *sch_ctx_ptr;
+       uint32_t                        query_status_fence_offs;
+       uint64_t                        query_status_fence_gpu_addr;
+       uint64_t                        *query_status_fence_ptr;
 
        /* ip specific functions */
        const struct amdgpu_mes_funcs   *funcs;
index 447bee159089655720c0b35ed54c092048d0cc7a..6ba0c04f7fb5426c19cfd924e48ed898f9d936eb 100644 (file)
@@ -237,6 +237,8 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
        mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
        mes_set_hw_res_pkt.paging_vmid = 0;
        mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
+       mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
+               mes->query_status_fence_gpu_addr;
 
        for (i = 0; i < MAX_COMPUTE_PIPES; i++)
                mes_set_hw_res_pkt.compute_hqd_mask[i] =