media: mt9p031: Make pixel clock polarity configurable by DT
authorChristian Hemp <c.hemp@phytec.de>
Mon, 26 Jul 2021 07:35:14 +0000 (09:35 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Thu, 30 Sep 2021 08:07:35 +0000 (10:07 +0200)
Evaluate the desired pixel clock polarity from the device tree.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/Kconfig
drivers/media/i2c/mt9p031.c
include/media/i2c/mt9p031.h

index 08feb3e..c26b05e 100644 (file)
@@ -1229,6 +1229,7 @@ config VIDEO_MT9P031
        select MEDIA_CONTROLLER
        select VIDEO_V4L2_SUBDEV_API
        select VIDEO_APTINA_PLL
+       select V4L2_FWNODE
        help
          This is a Video4Linux2 sensor driver for the Aptina
          (Micron) mt9p031 5 Mpixel camera.
index 9dea7c8..ea90aff 100644 (file)
@@ -27,6 +27,7 @@
 #include <media/v4l2-async.h>
 #include <media/v4l2-ctrls.h>
 #include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
 #include <media/v4l2-subdev.h>
 
 #include "aptina-pll.h"
@@ -372,6 +373,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
                return ret;
        }
 
+       /* Configure the pixel clock polarity */
+       if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) {
+               ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL,
+                               MT9P031_PIXEL_CLOCK_INVERT);
+               if (ret < 0)
+                       return ret;
+       }
+
        return v4l2_ctrl_handler_setup(&mt9p031->ctrls);
 }
 
@@ -1014,8 +1023,11 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
 static struct mt9p031_platform_data *
 mt9p031_get_pdata(struct i2c_client *client)
 {
-       struct mt9p031_platform_data *pdata;
+       struct mt9p031_platform_data *pdata = NULL;
        struct device_node *np;
+       struct v4l2_fwnode_endpoint endpoint = {
+               .bus_type = V4L2_MBUS_PARALLEL
+       };
 
        if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
                return client->dev.platform_data;
@@ -1024,6 +1036,9 @@ mt9p031_get_pdata(struct i2c_client *client)
        if (!np)
                return NULL;
 
+       if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
+               goto done;
+
        pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
        if (!pdata)
                goto done;
@@ -1031,6 +1046,9 @@ mt9p031_get_pdata(struct i2c_client *client)
        of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq);
        of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq);
 
+       pdata->pixclk_pol = !!(endpoint.bus.parallel.flags &
+                              V4L2_MBUS_PCLK_SAMPLE_RISING);
+
 done:
        of_node_put(np);
        return pdata;
index 7c29c53..f933cd0 100644 (file)
@@ -10,6 +10,7 @@ struct v4l2_subdev;
  * @target_freq: Pixel clock frequency
  */
 struct mt9p031_platform_data {
+       unsigned int pixclk_pol:1;
        int ext_freq;
        int target_freq;
 };