+2000-11-26 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * config/tc-m68hc11.c (build_indexed_byte): Print the offset in
+ the error message.
+ (get_operand): Fix analysis for movw/movb instructions.
+
2000-11-24 Nick Clifton <nickc@redhat.com>
* configure.in (xscale-elf): Add target.
if (*p == ',')
{
+ int possible_mode = M6811_OP_NONE;
+ char *old_input_line;
p++;
/* 68HC12 pre increment or decrement. */
{
if (*p == '-')
{
- mode = M6812_PRE_DEC;
+ possible_mode = M6812_PRE_DEC;
p++;
- if (current_architecture & cpu6811)
- as_bad (_("Pre-decrement mode is not valid for 68HC11"));
}
else if (*p == '+')
{
- mode = M6812_PRE_INC;
+ possible_mode = M6812_PRE_INC;
p++;
- if (current_architecture & cpu6811)
- as_bad (_("Pre-increment mode is not valid for 68HC11"));
}
p = skip_whites (p);
}
+ old_input_line = input_line_pointer;
input_line_pointer = p;
reg = register_name ();
+ /* Backtrack if we have a valid constant expression and
+ it does not correspond to the offset of the 68HC12 indexed
+ addressing mode (as in N,x). */
+ if (reg == REG_NONE && mode == M6811_OP_NONE
+ && possible_mode != M6811_OP_NONE)
+ {
+ oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
+ input_line_pointer = skip_whites (old_input_line);
+ return 1;
+ }
+
+ if (possible_mode != M6811_OP_NONE)
+ mode = possible_mode;
+
+ if ((current_architecture & cpu6811)
+ && possible_mode != M6811_OP_NONE)
+ as_bad (_("Pre-increment mode is not valid for 68HC11"));
/* Backtrack. */
if (which == 0 && opmode & M6812_OP_IDX_P2
&& reg != REG_X && reg != REG_Y
if (move_insn && !(val >= -16 && val <= 15))
{
- as_bad (_("Offset out of 5-bit range for movw/movb insn."));
+ as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
+ val);
return -1;
}
+2000-11-26 Stephane Carrez <Stephane.Carrez@worldnet.fr>
+
+ * gas/m68hc11/opers12.s: New test for movw operands.
+ * gas/m68hc11/opers12.d: Likewise.
+
2000-11-24 Nick Clifton <nickc@redhat.com>
* arm.exp: Run tests for xscale as well as arm.
0+0b6 <L1\+0xad> trap #64
0+0b8 <L1\+0xaf> trap #128
0+0ba <L1\+0xb1> trap #255
-0+0bc <L2> rts
+0+0bc <L2> movw 1,X, 2,X
+0+0c0 <L2\+0x4> movw 0+0ffff <L2\+0xff43>, 0000ffff <L2\+0xff43>
+0+0c6 <L2\+0xa> movw 0+0ffff <L2\+0xff43>, 1,X
+0+0cb <L2\+0xf> movw #0+0ffff <L2\+0xff43>, 1,X
+0+0d0 <L2\+0x14> movw 0+03 <start\+0x3>, 0+08 <start\+0x8>
+0+0d6 <L2\+0x1a> movw #0+03 <start\+0x3>, 0+03 <start\+0x3>
+0+0dc <L2\+0x20> movw #0+03 <start\+0x3>, 1,X
+0+0e1 <L2\+0x25> movw 0+03 <start\+0x3>, 1,X
+0+0e6 <L2\+0x2a> movw 0+03 <start\+0x3>, 2,X
+0+0eb <L2\+0x2f> movw 0+04 <start\+0x4>, -2,X
+0+0f0 <L2\+0x34> rts
+
trap #0x80
trap #255
L2:
+ movw 1,x,2,x
+ movw -1,-1
+ movw -1,1,x
+ movw #-1,1,x
+ movw 3,8
+ movw #3,3
+ movw #3,1,x
+ movw 3,1,x
+ movw 3,+2,x
+ movw 4,-2,x
rts