+2016-01-25 Bilyan Borisov <bilyan.borisov@arm.com>
+
+ * config/aarch64/arm_neon.h (vcvt_s64_f64): New intrinsic.
+ (vcvt_u64_f64): Likewise.
+ (vcvta_s64_f64): Likewise.
+ (vcvta_u64_f64): Likewise.
+ (vcvtm_s64_f64): Likewise.
+ (vcvtm_u64_f64): Likewise.
+ (vcvtn_s64_f64): Likewise.
+ (vcvtn_u64_f64): Likewise.
+ (vcvtp_s64_f64): Likewise.
+ (vcvtp_u64_f64): Likewise.
+
2016-01-25 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.c (TARGET_DWARF_REGISTER_SPAN): Define.
return __builtin_aarch64_lbtruncuv4sfv4si_us (__a);
}
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvt_s64_f64 (float64x1_t __a)
+{
+ return (int64x1_t) {vcvtd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvt_u64_f64 (float64x1_t __a)
+{
+ return (uint64x1_t) {vcvtd_u64_f64 (__a[0])};
+}
+
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
vcvtq_s64_f64 (float64x2_t __a)
{
return __builtin_aarch64_lrounduv4sfv4si_us (__a);
}
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvta_s64_f64 (float64x1_t __a)
+{
+ return (int64x1_t) {vcvtad_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvta_u64_f64 (float64x1_t __a)
+{
+ return (uint64x1_t) {vcvtad_u64_f64 (__a[0])};
+}
+
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
vcvtaq_s64_f64 (float64x2_t __a)
{
return __builtin_aarch64_lflooruv4sfv4si_us (__a);
}
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtm_s64_f64 (float64x1_t __a)
+{
+ return (int64x1_t) {vcvtmd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtm_u64_f64 (float64x1_t __a)
+{
+ return (uint64x1_t) {vcvtmd_u64_f64 (__a[0])};
+}
+
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
vcvtmq_s64_f64 (float64x2_t __a)
{
return __builtin_aarch64_lfrintnuv4sfv4si_us (__a);
}
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtn_s64_f64 (float64x1_t __a)
+{
+ return (int64x1_t) {vcvtnd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtn_u64_f64 (float64x1_t __a)
+{
+ return (uint64x1_t) {vcvtnd_u64_f64 (__a[0])};
+}
+
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
vcvtnq_s64_f64 (float64x2_t __a)
{
return __builtin_aarch64_lceiluv4sfv4si_us (__a);
}
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vcvtp_s64_f64 (float64x1_t __a)
+{
+ return (int64x1_t) {vcvtpd_s64_f64 (__a[0])};
+}
+
+__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__))
+vcvtp_u64_f64 (float64x1_t __a)
+{
+ return (uint64x1_t) {vcvtpd_u64_f64 (__a[0])};
+}
+
__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
vcvtpq_s64_f64 (float64x2_t __a)
{
+2016-01-25 Bilyan Borisov <bilyan.borisov@arm.com>
+
+ * gcc.target/aarch64/simd/vcvt_s64_f64_1.c: New.
+ * gcc.target/aarch64/simd/vcvt_u64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvta_s64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvta_u64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtm_s64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtm_u64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtn_s64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtn_u64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtp_s64_f64_1.c: Likewise.
+ * gcc.target/aarch64/simd/vcvtp_u64_f64_1.c: Likewise.
+
2016-01-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/69376
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ int64x1_t b1 = vcvt_s64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ volatile float64x1_t a2 = {-0.5};
+ int64x1_t b2 = vcvt_s64_f64 (a2);
+
+ if (b2[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtzs\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ uint64x1_t b1 = vcvt_u64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtzu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ int64x1_t b1 = vcvta_s64_f64 (a);
+
+ if (b1[0] != 1)
+ abort ();
+
+ volatile float64x1_t a2 = {-0.5};
+ int64x1_t b2 = vcvta_s64_f64 (a2);
+
+ if (b2[0] != -1)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtas\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ uint64x1_t b1 = vcvta_u64_f64 (a);
+
+ if (b1[0] != 1)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtau\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ int64x1_t b1 = vcvtm_s64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ volatile float64x1_t a2 = {-0.5};
+ int64x1_t b2 = vcvtm_s64_f64 (a2);
+
+ if (b2[0] != -1)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtms\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ uint64x1_t b1 = vcvtm_u64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtmu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ int64x1_t b1 = vcvtn_s64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ volatile float64x1_t a2 = {-0.5};
+ int64x1_t b2 = vcvtn_s64_f64 (a2);
+
+ if (b2[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtns\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ uint64x1_t b1 = vcvtn_u64_f64 (a);
+
+ if (b1[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtnu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ int64x1_t b1 = vcvtp_s64_f64 (a);
+
+ if (b1[0] != 1)
+ abort ();
+
+ volatile float64x1_t a2 = {-0.5};
+ int64x1_t b2 = vcvtp_s64_f64 (a2);
+
+ if (b2[0] != 0)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtps\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-save-temps -O3" } */
+
+#include "arm_neon.h"
+
+extern void abort ();
+
+int
+main()
+{
+ volatile float64x1_t a = {0.5};
+ uint64x1_t b1 = vcvtp_u64_f64 (a);
+
+ if (b1[0] != 1)
+ abort ();
+
+ return 0;
+}
+/* { dg-final { scan-assembler "fcvtpu\[ \t\]+\[xX\]\[0-9\]+, ?\[dD\]\[0-9\]+\n" } } */
projects / platform / upstream / gcc.git / commitdiff