vsx-vector-6-be.p7.c: Rename this file to vsx-vector-6.p7.c.

gcc/testsuite/ChangeLog:

2018-06-08  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to
	vsx-vector-6.p7.c.
	* gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename this file to
	vsx-vector-6.p9.c.
	* gcc.target/powerpc/vsx-vector-6-be.p8.c: Move instruction counts
	for BE system that are different then for an LE system from this file
	into vsx-vector-6-le.c using be target qualifier.  Remove this file.
	* gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for
	the various instruction counts.  Rename file to	vsx-vector-6.p8.c.

From-SVN: r261333

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d0c9e04..af9b5d4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2018-06-08  Carl Love  <cel@us.ibm.com>
+
+       * gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to
+       vsx-vector-6.p7.c.
+       * gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename this file to
+       vsx-vector-6.p9.c.
+       * gcc.target/powerpc/vsx-vector-6-be.p8.c: Move instruction counts
+       for BE system that are different then for an LE system from this file
+       into vsx-vector-6-le.c using be target qualifier.  Remove this file.
+       * gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for
+       the various instruction counts.  Rename file to vsx-vector-6.p8.c.
+
 2018-06-08  Martin Liska  <mliska@suse.cz>
 
        * gcc.dg/ipa/ipa-icf-38.c: Scan optimized tree dump.

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c
deleted file mode 100644 (file)
index 3b81df8..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2 -mcpu=power8" } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-
-
-/* Expected instruction counts for Big Endian */
-
-/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */
-/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
-/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
-/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
-/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
-/* { dg-final { scan-assembler-times "xxland" 13 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 2 } } */
-/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
-/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
similarity index 60%
rename from gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c
rename to gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
index 835b24f..66ec064 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
@@ -1,21 +1,28 @@
-/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-options "-mvsx -O2 -mcpu=power7" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
 
 
-/* Expected instruction counts for Big Endian */
+/* Expected instruction counts for Power 7 */
 
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */
 /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
 /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
similarity index 71%
rename from gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
rename to gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
index be5b972..82fd45e 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
@@ -1,23 +1,31 @@
-/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-options "-mvsx -O2 -mcpu=power8" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
 
-/* Expected instruction counts for Little Endian targeting Power8. */
+
+/* Expected instruction counts for Power 8.  */
 
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 8 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
+
 /* We generate xxlor instructions for many reasons other than or'ing vector
    operands or calling __builtin_vec_or(), which  means we cannot rely on
    their usage counts being stable.  Therefore, we just ensure at least one
    xxlor instruction was generated.  */
 /* { dg-final { scan-assembler "xxlor" } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 } } */
+
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */
 /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
similarity index 93%
rename from gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c
rename to gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
index c2427b8..0fcd153 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
@@ -1,19 +1,21 @@
-/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mvsx -O2 -mcpu=power9" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
 
-/* Expected instruction counts for Little Endian targeting Power9. */
+/* Expected instruction counts for Power9. */
 
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 7 } } */
+
 /* We generate xxlor instructions for many reasons other than or'ing vector
    operands or calling __builtin_vec_or(), which  means we cannot rely on
    their usage counts being stable.  Therefore, we just ensure at least one
    xxlor instruction was generated.  */
 /* { dg-final { scan-assembler "xxlor" } } */
+
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
 /* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
 /* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */