GFX-Display: fixed the issue that pipe B vblank interrupt couldn't be re-enabled.

BZ: 23164

Whend display driver enables pipe B vblank interrupt after it's enabled in DPMS on,
it would be disabled as it's masked out by the incorrectly defined pipe event mask.

Fixed the issue by adding the bits enabling interrupts (at least bit 17) to the pipe
event mask for PIPExSTAT register.

Change-Id: I782ba606d9ed029a95ae37b8a8d86a8443c7bc1c
Signed-off-by: Austin Hu <austin.hu@intel.com>
Reviewed-on: http://android.intel.com:8080/34810
Reviewed-by: Tong, BoX <box.tong@intel.com>
Tested-by: Tong, BoX <box.tong@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/staging/mrst/drv/psb_intel_reg.h b/drivers/staging/mrst/drv/psb_intel_reg.h
index bd4154f..d1570f8 100644 (file)
--- a/drivers/staging/mrst/drv/psb_intel_reg.h
+++ b/drivers/staging/mrst/drv/psb_intel_reg.h
@@ -432,7 +432,8 @@
 #define PIPE_HDMI_AUDIO_UNDERRUN             (1UL<<26)
 #define PIPE_HDMI_AUDIO_BUFFER_DONE          (1UL<<27)
 #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | PIPE_HDMI_AUDIO_BUFFER_DONE)
-#define PIPE_EVENT_MASK (BIT29|BIT28|BIT27|BIT26|BIT24|BIT23|BIT22|BIT21|BIT20|BIT16)
+#define PIPE_EVENT_MASK (BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21 \
+               |BIT20|BIT18|BIT17|BIT16)
 #define PIPE_VBLANK_MASK (BIT25|BIT24|BIT18|BIT17)
 #define HISTOGRAM_INT_CONTROL          0x61268
 #define HISTOGRAM_BIN_DATA             0X61264