clk: mediatek: add CLK_XTAL support for clock driver

This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 207a4c6..4303300 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
                rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
                break;
 
+       case CLK_PARENT_XTAL:
        default:
                rate = priv->tree->xtal_rate;
        }
@@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
                rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
                                                priv->parent);
                break;
+       case CLK_PARENT_XTAL:
+               rate = priv->tree->xtal_rate;
+               break;
        default:
                rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
        }

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index e7c61ae..48ce164 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -29,7 +29,8 @@
 #define CLK_PARENT_APMIXED             BIT(4)
 #define CLK_PARENT_TOPCKGEN            BIT(5)
 #define CLK_PARENT_INFRASYS            BIT(6)
-#define CLK_PARENT_MASK                        GENMASK(6, 4)
+#define CLK_PARENT_XTAL                        BIT(7)
+#define CLK_PARENT_MASK                        GENMASK(7, 4)
 
 #define ETHSYS_HIFSYS_RST_CTRL_OFS     0x34