clk: tegra: add suspend/resume function for tegra_cpu_car_ops
authorJoseph Lo <josephl@nvidia.com>
Wed, 3 Jul 2013 09:50:44 +0000 (17:50 +0800)
committerStephen Warren <swarren@nvidia.com>
Fri, 19 Jul 2013 16:08:08 +0000 (10:08 -0600)
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
drivers/clk/tegra/clk-tegra114.c

index b6015cb..f74ed19 100644 (file)
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS    0x470
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+       u32 clk_csite_src;
+} tegra114_cpu_clk_sctx;
+#endif
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2142,9 +2148,29 @@ static void tegra114_disable_cpu_clock(u32 cpu)
        /* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra114_cpu_clock_suspend(void)
+{
+       /* switch coresite to clk_m, save off original source */
+       tegra114_cpu_clk_sctx.clk_csite_src =
+                               readl(clk_base + CLK_SOURCE_CSITE);
+       writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
+}
+
+static void tegra114_cpu_clock_resume(void)
+{
+       writel(tegra114_cpu_clk_sctx.clk_csite_src,
+                                       clk_base + CLK_SOURCE_CSITE);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
        .wait_for_reset = tegra114_wait_cpu_in_reset,
        .disable_clock  = tegra114_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+       .suspend        = tegra114_cpu_clock_suspend,
+       .resume         = tegra114_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {