bool Replace = false;
SDValue N0 = Op.getOperand(0);
- SDValue N1 = Op.getOperand(1);
if (Opc == ISD::SRA)
N0 = SExtPromoteOperand(N0, PVT);
else if (Opc == ISD::SRL)
return SDValue();
SDLoc DL(Op);
+ SDValue N1 = Op.getOperand(1);
SDValue RV =
DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare void @use(<1 x i16>)
+
+define i16 @basic(i16* %p) {
+; CHECK-LABEL: basic:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movswl (%rdi), %eax
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: sarl %cl, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %v = load i16, i16* %p
+ %s = ashr i16 %v, %v
+ ret i16 %s
+}
+
+define void @crash(i1 %cond, <1 x i16>* %p) {
+; CHECK-LABEL: crash:
+; CHECK: # %bb.0:
+; CHECK-NEXT: .p2align 4, 0x90
+; CHECK-NEXT: .LBB1_1: # %loop
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: jne .LBB1_1
+; CHECK-NEXT: # %bb.2: # %exit
+; CHECK-NEXT: retq
+ br label %loop
+
+loop:
+ %v = load <1 x i16>, <1 x i16>* %p, align 2
+ %ins = insertelement <4 x double> zeroinitializer, double 0.000000e+00, i32 0
+ %cmp = fcmp uge <4 x double> %ins, zeroinitializer
+ %ashr = ashr <1 x i16> %v, %v
+ %shuf = shufflevector <4 x i1> %cmp, <4 x i1> zeroinitializer, <4 x i32> zeroinitializer
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ %use1 = add <4 x i1> %shuf, zeroinitializer
+ %use2 = add <1 x i16> %ashr, zeroinitializer
+ ret void
+}