u32 *boot_loc_ptr_l, *boot_loc_ptr_h;
int ret;
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
#else
#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
#ifndef __ARM_PSCI_H__
#define __ARM_PSCI_H__
+#define ARM_PSCI_VER_1_0 (0x00010000)
+#define ARM_PSCI_VER_0_2 (0x00000002)
+
/* PSCI 0.1 interface */
#define ARM_PSCI_FN_BASE 0x95c1ba5e
#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n))
#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
- char *psci_compt;
int tmp;
nodeoff = fdt_path_offset(fdt, "/cpus");
fdt_setprop_string(fdt, tmp, "enable-method", "psci");
}
- /*
- * The PSCI node might be called "/psci" or might be called something
- * else but contain either of the compatible strings
- * "arm,psci"/"arm,psci-0.2"
- */
nodeoff = fdt_path_offset(fdt, "/psci");
if (nodeoff >= 0)
goto init_psci_node;
- nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci");
- if (nodeoff >= 0)
- goto init_psci_node;
-
- nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-0.2");
- if (nodeoff >= 0)
- goto init_psci_node;
-
- nodeoff = fdt_node_offset_by_compatible(fdt, -1, "arm,psci-1.0");
- if (nodeoff >= 0)
- goto init_psci_node;
-
nodeoff = fdt_path_offset(fdt, "/");
if (nodeoff < 0)
return nodeoff;
init_psci_node:
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
+#elif defined(CONFIG_ARMV7_PSCI_1_0)
+ psci_ver = ARM_PSCI_VER_1_0;
#endif
switch (psci_ver) {
- case 0x00010000:
- psci_compt = "arm,psci-1.0";
- break;
- case 0x00000002:
- psci_compt = "arm,psci-0.2";
- break;
+ case ARM_PSCI_VER_1_0:
+ tmp = fdt_setprop_string(fdt, nodeoff,
+ "compatible", "arm,psci-1.0");
+ if (tmp)
+ return tmp;
+ case ARM_PSCI_VER_0_2:
+ tmp = fdt_appendprop_string(fdt, nodeoff,
+ "compatible", "arm,psci-0.2");
+ if (tmp)
+ return tmp;
default:
- psci_compt = "arm,psci";
+ /*
+ * The Secure firmware framework isn't able to support PSCI version 0.1.
+ */
+#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
+ tmp = fdt_appendprop_string(fdt, nodeoff,
+ "compatible", "arm,psci");
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
+ ARM_PSCI_FN_CPU_SUSPEND);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off",
+ ARM_PSCI_FN_CPU_OFF);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on",
+ ARM_PSCI_FN_CPU_ON);
+ if (tmp)
+ return tmp;
+ tmp = fdt_setprop_u32(fdt, nodeoff, "migrate",
+ ARM_PSCI_FN_MIGRATE);
+ if (tmp)
+ return tmp;
+#endif
break;
}
- tmp = fdt_setprop_string(fdt, nodeoff, "compatible", psci_compt);
- if (tmp)
- return tmp;
tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc");
if (tmp)
return tmp;
-#ifdef CONFIG_ARMV7_PSCI
- tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend",
- ARM_PSCI_FN_CPU_SUSPEND);
- if (tmp)
- return tmp;
- tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF);
- if (tmp)
- return tmp;
- tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON);
- if (tmp)
- return tmp;
- tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE);
- if (tmp)
- return tmp;
-#endif
#endif
return 0;
}
#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
-#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */
F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
B4860QDS_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/B4860QDS_SECURE_BOOT_defconfig
F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig
CORENET_DS_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
F: configs/ls1021atwr_sdcard_ifc_defconfig
F: configs/ls1021atwr_sdcard_qspi_defconfig
F: configs/ls1021atwr_qspi_defconfig
+
+M: Sumit Garg <sumit.garg@nxp.com>
+S: Maintained
+F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
F: configs/ls1043ardb_sdcard_defconfig
LS1043A_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/ls1043ardb_SECURE_BOOT_defconfig
F: configs/T1040QDS_DDR4_defconfig
T1040QDS_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/T1040QDS_SECURE_BOOT_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
T1040RDB_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/T1040RDB_SECURE_BOOT_defconfig
F: configs/T1040D4RDB_SECURE_BOOT_defconfig
F: configs/T1042RDB_SECURE_BOOT_defconfig
F: configs/T1042D4RDB_SECURE_BOOT_defconfig
+
+M: Sumit Garg <sumit.garg@nxp.com>
+S: Maintained
+F: configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
T2080QDS_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/T2080QDS_SECURE_BOOT_defconfig
F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
T2080RDB_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/T2080RDB_SECURE_BOOT_defconfig
F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
T4160QDS_SECURE_BOOT BOARD
-M: Aneesh Bansal <aneesh.bansal@freescale.com>
+M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/T4160QDS_SECURE_BOOT_defconfig
F: configs/T4240QDS_SECURE_BOOT_defconfig
*/
static int do_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- uint32_t key_addr, src_addr, dst_addr, len;
+ ulong key_addr, src_addr, dst_addr, len;
uint8_t *km_ptr, *src_ptr, *dst_ptr;
int enc, ret = 0;
int ret, i = 0;
u32 *desc;
- printf("\nDecapsulating data to form blob\n");
+ printf("\nDecapsulating blob to get data\n");
desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
+ debug("Descriptor dump:\n");
for (i = 0; i < 14; i++)
- printf("%x\n", *(desc + i));
+ debug("Word[%d]: %08x\n", i, *(desc + i));
ret = run_descriptor_jr(desc);
if (ret)
printf("Error in Decapsulation %d\n", ret);
+ else
+ printf("Decapsulation Success\n");
free(desc);
return ret;
}
inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
+
+ debug("Descriptor dump:\n");
for (i = 0; i < 14; i++)
- printf("%x\n", *(desc + i));
+ debug("Word[%d]: %08x\n", i, *(desc + i));
ret = run_descriptor_jr(desc);
if (ret)
printf("Error in Encapsulation %d\n", ret);
+ else
+ printf("Encapsulation Success\n");
free(desc);
return ret;
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
- | ((wr_lat & 0x10) << 18)
+ | (((wr_lat & 0x10) >> 4) << 18)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
{
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg;
+ void *rx_addr = NULL;
mcr_reg = qspi_read32(priv->flags, ®s->mcr);
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+ rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
/* Read out the data directly from the AHB buffer. */
- memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
+ memcpy(rxbuf, rx_addr, len);
qspi_write32(priv->flags, ®s->mcr, mcr_reg);
}
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_BRDCFG_REG 0x04
#define QIXIS_LBMAP_SWITCH 6
-#define QIXIS_LBMAP_MASK 0xf7
+#define QIXIS_LBMAP_MASK 0x08
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x08
-#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
/* Command line configuration */
#define CONFIG_CMD_ENV
+#define CONFIG_MENU
+#define CONFIG_CMD_PXE
/* MMC */
#define CONFIG_MMC
#define SEC_FIRMWARE_ERET_ADDR_REVERT
#define CONFIG_ARMV8_PSCI
-#define CONFIG_SYS_LS_PPA_FW_IN_NOR
-#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#define CONFIG_SYS_LS_PPA_FW_IN_XIP
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
#endif
#endif
#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
-#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680
+#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
#define START_REFRESH 0x00000001