drm/i915/xehpsdv: Read correct RP_STATE_CAP register

The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-7-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index a3e69eba376f83db3941f19fe2c1c73e3ef5402d..3489f5f0cac10cd2e06f148a837d8ec907c11e27 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2141,7 +2141,9 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps)
        struct drm_i915_private *i915 = rps_to_i915(rps);
        struct intel_uncore *uncore = rps_to_uncore(rps);
 
-       if (IS_GEN9_LP(i915))
+       if (IS_XEHPSDV(i915))
+               return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
+       else if (IS_GEN9_LP(i915))
                return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
        else
                return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8db6e8ef1ad44325ad8d5201dd89cdc83a1ebc2..f79f02ee12db4a4c286093fa895cbde3f4af3e09 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4124,6 +4124,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   RPN_CAP_MASK         REG_GENMASK(23, 16)
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
+#define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
 
 /*
  * Logical Context regs