* archures.c, bfd-in2.h, mips-cpu.c : Added bfd_mach_mips4320.
done
fi
+vr4320_files="ChangeLog archures.c bfd-in2.h cpu-mips.c"
+if ( echo $* | grep keep\-vr4320 > /dev/null ) ; then
+ for i in $vr4320_files ; do
+ if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Keeping vr4320 stuff in $i
+ fi
+ fi
+ done
+else
+ for i in $vr4320_files ; do
+ if test ! -d $i && (grep sanitize-vr4320 $i > /dev/null) ; then
+ if [ -n "${verbose}" ] ; then
+ echo Removing traces of \"vr4320\" from $i...
+ fi
+ cp $i new
+ sed '/start\-sanitize\-vr4320/,/end-\sanitize\-vr4320/d' < $i > new
+ if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+ if [ -n "${verbose}" ] ; then
+ echo Caching $i in .Recover...
+ fi
+ mv $i .Recover
+ fi
+ mv new $i
+ fi
+ done
+fi
+
m32rx_files="ChangeLog archures.c bfd-in2.h elf32-m32r.c cpu-m32r.c"
if ( echo $* | grep keep\-m32rx > /dev/null ) ; then
for i in $m32rx_files ; do
+start-sanitize-vr4320
+Tue Mar 3 11:24:05 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips-cpu.c: Reorganize sanitization.
+
+ * archures.c, bfd-in2.h, mips-cpu.c : Added bfd_mach_mips4320.
+
+end-sanitize-vr4320
Mon Feb 23 19:31:19 1998 Ian Lance Taylor <ian@cygnus.com>
* configure.in: Add elf.lo to elf shell variable.
.#define bfd_mach_mips4400 4400
.#define bfd_mach_mips4600 4600
.#define bfd_mach_mips4650 4650
+. {* start-sanitize-vr4320 *}
+.#define bfd_mach_mips4320 4320
+. {* end-sanitize-4320 *}
. {* start-sanitize-tx49 *}
.#define bfd_mach_mips4900 4900
. {* end-sanitize-tx49 *}
. {* start-sanitize-sky *}
. {* The DVP is a machine within the mips architecture. *}
.#define bfd_mach_dvp_dma 42000
-.#define bfd_mach_dvp_pke 42001
+.#define bfd_mach_dvp_vif 42001
.#define bfd_mach_dvp_vu 42002
-.#define bfd_mach_dvp_gpuif 42003
+.#define bfd_mach_dvp_gif 42003
.#define bfd_mach_dvp_p(mach) ((mach) >= 42000 && (mach) <= 42003)
. {* end-sanitize-sky *}
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_arm_4T 6
. bfd_arch_ns32k, {* National Semiconductors ns32000 *}
. bfd_arch_w65, {* WDC 65816 *}
+. bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
. {* start-sanitize-tic80 *}
. bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
. {* end-sanitize-tic80 *}
extern const bfd_arch_info_type bfd_rs6000_arch;
extern const bfd_arch_info_type bfd_sh_arch;
extern const bfd_arch_info_type bfd_sparc_arch;
+extern const bfd_arch_info_type bfd_tic30_arch;
/* start-sanitize-tic80 */
extern const bfd_arch_info_type bfd_tic80_arch;
/* end-sanitize-tic80 */
-/* start-sanitize-sky */
-extern const bfd_arch_info_type bfd_txvu_arch;
-/* end-sanitize-sky */
extern const bfd_arch_info_type bfd_vax_arch;
extern const bfd_arch_info_type bfd_we32k_arch;
extern const bfd_arch_info_type bfd_z8k_arch;
&bfd_rs6000_arch,
&bfd_sh_arch,
&bfd_sparc_arch,
+ &bfd_tic30_arch,
/* start-sanitize-tic80 */
&bfd_tic80_arch,
/* end-sanitize-tic80 */
-/* start-sanitize-sky */
- &bfd_txvu_arch,
-/* end-sanitize-sky */
&bfd_vax_arch,
&bfd_we32k_arch,
&bfd_z8k_arch,
#define bfd_mach_mips4400 4400
#define bfd_mach_mips4600 4600
#define bfd_mach_mips4650 4650
+ /* start-sanitize-vr4320 */
+#define bfd_mach_mips4320 4320
+ /* start-sanitize-vr4320 */
/* start-sanitize-tx49 */
#define bfd_mach_mips4900 4900
/* end-sanitize-tx49 */
/* start-sanitize-sky */
/* The DVP is a machine within the mips architecture. */
#define bfd_mach_dvp_dma 42000
-#define bfd_mach_dvp_pke 42001
+#define bfd_mach_dvp_vif 42001
#define bfd_mach_dvp_vu 42002
-#define bfd_mach_dvp_gpuif 42003
+#define bfd_mach_dvp_gif 42003
#define bfd_mach_dvp_p(mach) ((mach) >= 42000 && (mach) <= 42003)
/* end-sanitize-sky */
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_arm_4T 6
bfd_arch_ns32k, /* National Semiconductors ns32000 */
bfd_arch_w65, /* WDC 65816 */
+ bfd_arch_tic30, /* Texas Instruments TMS320C30 */
/* start-sanitize-tic80 */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
/* end-sanitize-tic80 */
This is an 11-bit pc relative reloc. The recorded address is for the
lower instruction word, and the value is in 128 bit units. */
BFD_RELOC_MIPS_DVP_11_PCREL,
+
+/* This is a 27 bit address left shifted by 4. */
+ BFD_RELOC_MIPS_DVP_27_S4,
/* end-sanitize-sky */
/* This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
instruction. */
BFD_RELOC_MN10300_16_PCREL,
+
+/* This is a 8bit DP reloc for the tms320c30, where the most
+significant 8 bits of a 24 bit word are placed into the least
+significant 8 bits of the opcode. */
+ BFD_RELOC_TIC30_LDP,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *