The VisionFive2 board has jh7110 soc with u74 core, and it is
riscv64 cpu arch having rvf and rvd floating point extensions.
Set platform.core.cpu.arch and platform.core.fpu.arch features
with the cpu information.
The features are used in tct-systeminfo-tizen-tests of web tct.
Change-Id: I5a9a84bd233a409bf46c22b02848f1e4aefefe74
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
%tizen_hal_feature tizen.org/feature/usb.host true
%tizen_hal_feature tizen.org/feature/download true
%tizen_hal_feature tizen.org/feature/platform.core.abi riscv_64
+%tizen_hal_feature tizen.org/feature/platform.core.cpu.arch riscv64
%tizen_hal_feature tizen.org/feature/platform.core.cpu.arch.riscv32 false
%tizen_hal_feature tizen.org/feature/platform.core.cpu.arch.riscv64 true
+%tizen_hal_feature tizen.org/feature/platform.core.fpu.arch rvfd
### VISIONFIVE2-Power ###
%package sub2-Preset_boards-VISIONFIVE2_HAL_Backend-Power