spi: cadence-quadspi: Disable the DAC for Intel LGM SoC

On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfe

DAC bit resets to 1 so there is no need to explicitly set it.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Link: https://lore.kernel.org/r/20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index a03a8a4..8c5e838 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1384,10 +1384,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
        writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
               cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
 
-       /* Enable Direct Access Controller */
-       reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
-       reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
-       writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+       /* Disable direct access controller */
+       if (!cqspi->use_direct_mode) {
+               reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+               reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+               writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+       }
 
        cqspi_controller_enable(cqspi, 1);
 }
@@ -1675,6 +1677,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
        .quirks = CQSPI_NEEDS_WR_DELAY,
 };
 
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+       .quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
        {
                .compatible = "cdns,qspi-nor",
@@ -1690,6 +1696,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
        },
        {
                .compatible = "intel,lgm-qspi",
+               .data = &intel_lgm_qspi,
        },
        { /* end of table */ }
 };