drm/i915: Fix cs timestamp frequency for ctg/elk/ilk

On ilk the UDW of TIMESTAMP increments every 1000 ns,
LDW is mbz. In order to represent that we'd need 52 bits,
but we only have 32 bits. Even worse most things want to
only deal with 32 bits of timestamp. So let's just set
up the timestamp frequency as if we only had the UDW.

On ctg/elk 63:20 of TIMESTAMP increments every 1/4 ns, 19:0
are mbz. To make life simpler let's ignore the LDW and set up
timestamp frequency based on the UDW only (increments every
1024 ns).

v2: Rebase

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031135703.14670-2-ville.syrjala@linux.intel.com
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 3f656d3..ebb7a5b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -107,7 +107,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore)
        return freq;
 }
 
-static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
+static u32 gen6_read_clock_frequency(struct intel_uncore *uncore)
 {
        /*
         * PRMs say:
@@ -119,6 +119,26 @@ static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
        return 12500000;
 }
 
+static u32 gen5_read_clock_frequency(struct intel_uncore *uncore)
+{
+       /*
+        * 63:32 increments every 1000 ns
+        * 31:0 mbz
+        */
+       return 1000000000 / 1000;
+}
+
+static u32 g4x_read_clock_frequency(struct intel_uncore *uncore)
+{
+       /*
+        * 63:20 increments every 1/4 ns
+        * 19:0 mbz
+        *
+        * -> 63:32 increments every 1024 ns
+        */
+       return 1000000000 / 1024;
+}
+
 static u32 gen2_read_clock_frequency(struct intel_uncore *uncore)
 {
        /*
@@ -137,8 +157,12 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
                return gen11_read_clock_frequency(uncore);
        else if (GRAPHICS_VER(uncore->i915) >= 9)
                return gen9_read_clock_frequency(uncore);
-       else if (GRAPHICS_VER(uncore->i915) >= 5)
+       else if (GRAPHICS_VER(uncore->i915) >= 6)
+               return gen6_read_clock_frequency(uncore);
+       else if (GRAPHICS_VER(uncore->i915) == 5)
                return gen5_read_clock_frequency(uncore);
+       else if (IS_G4X(uncore->i915))
+               return g4x_read_clock_frequency(uncore);
        else
                return gen2_read_clock_frequency(uncore);
 }