(define_insn "altivec_lvsl"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 194))]
"TARGET_ALTIVEC"
"lvsl %0,%1,%2"
(define_insn "altivec_lvsr"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 195))]
"TARGET_ALTIVEC"
"lvsr %0,%1,%2"
(define_insn "altivec_lvebx"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 196))]
"TARGET_ALTIVEC"
"lvebx %0,%1,%2"
(define_insn "altivec_lvehx"
[(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V8HI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 197))]
"TARGET_ALTIVEC"
"lvehx %0,%1,%2"
(define_insn "altivec_lvewx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 198))]
"TARGET_ALTIVEC"
"lvewx %0,%1,%2"
(define_insn "altivec_lvxl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 199))]
"TARGET_ALTIVEC"
"lvxl %0,%1,%2"
(define_insn "altivec_lvx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:SI 1 "register_operand" "r")
+ (unspec:V4SI [(match_operand:SI 1 "register_operand" "b")
(match_operand:SI 2 "register_operand" "r")] 200))]
"TARGET_ALTIVEC"
"lvx %0,%1,%2"
[(set_attr "type" "vecload")])
+;; Parallel the STV*'s with unspecs because some of them have
+;; identical rtl but are different instructions-- and gcc gets confused.
+
(define_insn "altivec_stvx"
- [(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -16)))
- (match_operand:V4SI 2 "register_operand" "v"))]
+ [(parallel
+ [(set (mem:V4SI
+ (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
+ (match_operand:SI 1 "register_operand" "r"))
+ (const_int -16)))
+ (match_operand:V4SI 2 "register_operand" "v"))
+ (unspec [(const_int 0)] 201)])]
"TARGET_ALTIVEC"
"stvx %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvxl"
[(parallel
[(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
+ (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r"))
(const_int -16)))
(match_operand:V4SI 2 "register_operand" "v"))
- (unspec [(const_int 0)] 201)])]
+ (unspec [(const_int 0)] 202)])]
"TARGET_ALTIVEC"
"stvxl %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvebx"
[(parallel
[(set (mem:V16QI
- (plus:SI (match_operand:SI 0 "register_operand" "r")
+ (plus:SI (match_operand:SI 0 "register_operand" "b")
(match_operand:SI 1 "register_operand" "r")))
(match_operand:V16QI 2 "register_operand" "v"))
- (unspec [(const_int 0)] 202)])]
+ (unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC"
"stvebx %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvehx"
- [(set (mem:V8HI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -2)))
- (match_operand:V8HI 2 "register_operand" "v"))]
+ [(parallel
+ [(set (mem:V8HI
+ (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
+ (match_operand:SI 1 "register_operand" "r"))
+ (const_int -2)))
+ (match_operand:V8HI 2 "register_operand" "v"))
+ (unspec [(const_int 0)] 204)])]
"TARGET_ALTIVEC"
"stvehx %2,%0,%1"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvewx"
- [(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -4)))
- (match_operand:V4SI 2 "register_operand" "v"))]
+ [(parallel
+ [(set (mem:V4SI
+ (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
+ (match_operand:SI 1 "register_operand" "r"))
+ (const_int -4)))
+ (match_operand:V4SI 2 "register_operand" "v"))
+ (unspec [(const_int 0)] 205)])]
"TARGET_ALTIVEC"
"stvewx %2,%0,%1"
[(set_attr "type" "vecstore")])