config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config SYS_DCACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+ int
+ default 0
+ help
+ The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+ def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+ SYS_CACHELINE_SIZE = 0
+ help
+ Select this (or let it be auto-selected by not defining any cache
+ sizes) in order to allow U-Boot to automatically detect the sizes
+ of caches at runtime. This has a small cost in code size & runtime
+ so if you know the cache configuration for your system at compile
+ time it would be beneficial to configure it.
+
config MIPS_L1_CACHE_SHIFT_4
bool
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
static inline unsigned long icache_line_size(void)
{
*
*/
LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else
config SYS_TEXT_BASE
default 0xbfc00000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
menu "dbau1x00 board options"
choice
config SYS_TEXT_BASE
default 0x87000000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
menu "vct board options"
choice
config SYS_TEXT_BASE
default 0x83800000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
config SYS_TEXT_BASE
default 0x9f000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
config SYS_TEXT_BASE
default 0x9f000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
default 0xbfc00000 if 32BIT
default 0xffffffffbfc00000 if 64BIT
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
config SYS_TEXT_BASE
default 0xa1000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif /* CONFIG_DBAU1550 */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* BOOTP options
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
#endif /* CONFIG_VCT_ONENAND */
/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
* I2C/EEPROM
*/
#define CONFIG_SYS_I2C