clk: imx6ul: add mmdc1 ipg clock
authorAnson Huang <Anson.Huang@nxp.com>
Fri, 31 Aug 2018 07:53:13 +0000 (15:53 +0800)
committerStephen Boyd <sboyd@kernel.org>
Wed, 17 Oct 2018 18:15:20 +0000 (11:15 -0700)
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into
clock tree for clock management.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/imx/clk-imx6ul.c
include/dt-bindings/clock/imx6ul-clock.h

index 361b43f..fd60d15 100644 (file)
@@ -408,6 +408,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
        clks[IMX6UL_CLK_WDOG1]          = imx_clk_gate2("wdog1",        "ipg",          base + 0x74,    16);
        clks[IMX6UL_CLK_MMDC_P0_FAST]   = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74,  20, CLK_IS_CRITICAL);
        clks[IMX6UL_CLK_MMDC_P0_IPG]    = imx_clk_gate2_flags("mmdc_p0_ipg",    "ipg",          base + 0x74,    24, CLK_IS_CRITICAL);
+       clks[IMX6UL_CLK_MMDC_P1_IPG]    = imx_clk_gate2("mmdc_p1_ipg",  "ipg",          base + 0x74,    26);
        clks[IMX6UL_CLK_AXI]            = imx_clk_gate_flags("axi",     "axi_podf",     base + 0x74,    28, CLK_IS_CRITICAL);
 
        /* CCGR4 */
index f8e0476..f718aac 100644 (file)
 #define IMX6UL_CLK_GPIO3               246
 #define IMX6UL_CLK_GPIO4               247
 #define IMX6UL_CLK_GPIO5               248
+#define IMX6UL_CLK_MMDC_P1_IPG         249
 
-#define IMX6UL_CLK_END                 249
+#define IMX6UL_CLK_END                 250
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */