drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flag

[Why]

DCN21 is stable enough to be build by default. So drop the flags.

[How]

Remove them using the unifdef tool. The following commands were executed
in sequence:

$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';'
$ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';'

In addition:

* Remove from kconfig, and replace any dependencies with DCN1_0.
* Remove from any makefiles.
* Fix and cleanup Renoir definitions in dal_asic_id.h
* Expand DCN1 ifdef to include DCN21 code in the following files:
    * clk_mgr/clk_mgr.c: dc_clk_mgr_create()
    * core/dc_resources.c: dc_create_resource_pool()
    * gpio/hw_factory.c: dal_hw_factory_init()
    * gpio/hw_translate.c: dal_hw_translate_init()

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1b865d7..329bd37 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2603,8 +2603,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
        case CHIP_NAVI10:
        case CHIP_NAVI14:
        case CHIP_NAVI12:
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case CHIP_RENOIR:
 #endif
                return amdgpu_dc != 0;

diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 0b4c71d..b5a9bfe 100644 (file)
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -15,23 +15,7 @@ config DRM_AMD_DC
 config DRM_AMD_DC_DCN1_0
        def_bool n
        help
-         RV and NV family support for display engine
-
-config DRM_AMD_DC_DCN2_1
-       bool "DCN 2.1 family"
-       depends on DRM_AMD_DC && X86
-       help
-         Choose this option if you want to have
-         Renoir support for display engine
-
-config DRM_AMD_DC_DSC_SUPPORT
-       bool "DSC support"
-       default y
-       depends on DRM_AMD_DC && X86
-       depends on DRM_AMD_DC_DCN1_0
-       help
-         Choose this option if you want to have
-         Dynamic Stream Compression support
+         Raven, Navi and Renoir family support for display engine
 
 config DRM_AMD_DC_HDCP
        bool "Enable HDCP support in DC"

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6c986d4..ad21240 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2756,9 +2756,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
        case CHIP_NAVI12:
        case CHIP_NAVI10:
        case CHIP_NAVI14:
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case CHIP_RENOIR:
-#endif
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -2922,13 +2920,11 @@ static int dm_early_init(void *handle)
                adev->mode_info.num_hpd = 5;
                adev->mode_info.num_dig = 5;
                break;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case CHIP_RENOIR:
                adev->mode_info.num_crtc = 4;
                adev->mode_info.num_hpd = 4;
                adev->mode_info.num_dig = 4;
                break;
-#endif
        default:
                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
                return -EINVAL;
@@ -3224,9 +3220,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
            adev->asic_type == CHIP_NAVI10 ||
            adev->asic_type == CHIP_NAVI14 ||
            adev->asic_type == CHIP_NAVI12 ||
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
            adev->asic_type == CHIP_RENOIR ||
-#endif
            adev->asic_type == CHIP_RAVEN) {
                /* Fill GFX9 params */
                tiling_info->gfx9.num_pipes =

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 118488e..229788b 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -891,7 +891,6 @@ enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
        return PP_SMU_RESULT_FAIL;
 }
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 enum pp_smu_status pp_rn_get_dpm_clock_table(
                struct pp_smu *pp, struct dpm_clocks *clock_table)
 {
@@ -973,7 +972,6 @@ enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
 
        return PP_SMU_RESULT_OK;
 }
-#endif
 
 void dm_pp_get_funcs(
                struct dc_context *ctx,
@@ -1018,14 +1016,12 @@ void dm_pp_get_funcs(
                funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
                break;
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
        case DCN_VERSION_2_1:
                funcs->ctx.ver = PP_SMU_VER_RN;
                funcs->rn_funcs.pp_smu.dm = ctx;
                funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
                funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
                break;
-#endif
        default:
                DRM_ERROR("smu version is not supported !\n");
                break;

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 38ef297..3821311 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -29,9 +29,6 @@ ifdef CONFIG_DRM_AMD_DC_DCN1_0
 DC_LIBS += dcn20
 DC_LIBS += dsc
 DC_LIBS += dcn10 dml
-endif
-
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
 DC_LIBS += dcn21
 endif
 

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 45bb2bd..47bb802 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -65,11 +65,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
        case DCN_VERSION_2_0:
                *h = dal_cmd_tbl_helper_dce112_get_table2();
                return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case DCN_VERSION_2_1:
                *h = dal_cmd_tbl_helper_dce112_get_table2();
                return true;
-#endif
        case DCE_VERSION_12_0:
        case DCE_VERSION_12_1:
                *h = dal_cmd_tbl_helper_dce112_get_table2();

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 9f15817..de01543 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -81,9 +81,7 @@ CLK_MGR_DCN20 = dcn20_clk_mgr.o
 AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
-endif
 
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
 ###############################################################################
 # DCN21
 ###############################################################################

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 76b4831..740d92b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -37,9 +37,7 @@
 #include "dcn10/rv1_clk_mgr.h"
 #include "dcn10/rv2_clk_mgr.h"
 #include "dcn20/dcn20_clk_mgr.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #include "dcn21/rn_clk_mgr.h"
-#endif
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -136,12 +134,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
        case FAMILY_RV:
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
                if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
                        rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
                        break;
                }
-#endif /* DCN2_1 */
                if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
                        rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
                        break;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e7e552f..30e42cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -705,10 +705,8 @@ static bool construct(struct dc *dc,
        if (!dc->clk_mgr)
                goto fail;
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
        if (dc->res_pool->funcs->update_bw_bounding_box)
                dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
-#endif
 
        /* Creation of current_state must occur after dc->dml
         * is initialized in dc_create_resource_pool because

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6e20c76..162e512 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -50,9 +50,7 @@
 #include "dcn10/dcn10_resource.h"
 #endif
 #include "dcn20/dcn20_resource.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #include "dcn21/dcn21_resource.h"
-#endif
 #include "dce120/dce120_resource.h"
 
 #define DC_LOGGER_INIT(logger)
@@ -102,10 +100,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
                dc_version = DCN_VERSION_1_0;
                if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_1_01;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
                if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_2_1;
-#endif
                break;
 #endif
 
@@ -168,12 +164,10 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        case DCN_VERSION_2_0:
                res_pool = dcn20_create_resource_pool(init_data, dc);
                break;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case DCN_VERSION_2_1:
                res_pool = dcn21_create_resource_pool(init_data, dc);
                break;
 #endif
-#endif
 
        default:
                break;

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 102a55d..a6c40c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -401,9 +401,7 @@ struct dc_debug_options {
        bool dmub_command_table; /* for testing only */
        struct dc_bw_validation_profile bw_val_profile;
        bool disable_fec;
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
        bool disable_48mhz_pwrdwn;
-#endif
        /* This forces a hard min on the DCFCLK requested to SMU/PP
         * watermarks are not affected.
         */

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 5b4a29e..8d0d07d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -76,7 +76,6 @@
                SRII(PIXEL_RATE_CNTL, OTG, 4),\
                SRII(PIXEL_RATE_CNTL, OTG, 5)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
                SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
                SRII(PHASE, DP_DTO, 0),\
@@ -91,7 +90,6 @@
                SRII(PIXEL_RATE_CNTL, OTG, 1),\
                SRII(PIXEL_RATE_CNTL, OTG, 2),\
                SRII(PIXEL_RATE_CNTL, OTG, 3)
-#endif
 
 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
        CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 4144b10..d01fb2f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -440,7 +440,6 @@ static bool dcn10_dmcu_init(struct dmcu *dmcu)
        return status;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 static bool dcn21_dmcu_init(struct dmcu *dmcu)
 {
        struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
@@ -452,7 +451,6 @@ static bool dcn21_dmcu_init(struct dmcu *dmcu)
 
        return dcn10_dmcu_init(dmcu);
 }
-#endif
 
 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
                unsigned int start_offset,
@@ -834,7 +832,6 @@ static const struct dmcu_funcs dcn20_funcs = {
        .unlock_phy = dcn20_unlock_phy
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 static const struct dmcu_funcs dcn21_funcs = {
        .dmcu_init = dcn21_dmcu_init,
        .load_iram = dcn10_dmcu_load_iram,
@@ -848,7 +845,6 @@ static const struct dmcu_funcs dcn21_funcs = {
        .unlock_phy = dcn20_unlock_phy
 };
 #endif
-#endif
 
 static void dce_dmcu_construct(
        struct dce_dmcu *dmcu_dce,
@@ -952,7 +948,6 @@ struct dmcu *dcn20_dmcu_create(
        return &dmcu_dce->base;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 struct dmcu *dcn21_dmcu_create(
        struct dc_context *ctx,
        const struct dce_dmcu_registers *regs,
@@ -974,7 +969,6 @@ struct dmcu *dcn21_dmcu_create(
        return &dmcu_dce->base;
 }
 #endif
-#endif
 
 void dce_dmcu_destroy(struct dmcu **dmcu)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 8927789..5e044c2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -272,13 +272,11 @@ struct dmcu *dcn20_dmcu_create(
        const struct dce_dmcu_shift *dmcu_shift,
        const struct dce_dmcu_mask *dmcu_mask);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 struct dmcu *dcn21_dmcu_create(
        struct dc_context *ctx,
        const struct dce_dmcu_registers *regs,
        const struct dce_dmcu_shift *dmcu_shift,
        const struct dce_dmcu_mask *dmcu_mask);
-#endif
 
 void dce_dmcu_destroy(struct dmcu **dmcu);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index f31eea1..ebe8f9a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -276,7 +276,6 @@
        SR(DC_IP_REQUEST_CNTL), \
        BL_REG_LIST()
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define HWSEQ_DCN21_REG_LIST()\
        HWSEQ_DCN_REG_LIST(), \
        HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
@@ -327,7 +326,6 @@
        SR(D6VGA_CONTROL), \
        SR(DC_IP_REQUEST_CNTL), \
        BL_REG_LIST()
-#endif
 
 struct dce_hwseq_registers {
 
@@ -635,7 +633,6 @@ struct dce_hwseq_registers {
        HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
        HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
        HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
        HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
@@ -678,7 +675,6 @@ struct dce_hwseq_registers {
        HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
        HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
        HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
-#endif
 
 #define HWSEQ_REG_FIELD_LIST(type) \
        type DCFE_CLOCK_ENABLE; \

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 69d903d..af57751 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -121,7 +121,6 @@ struct dcn_hubbub_registers {
        uint32_t DCN_VM_AGP_BASE;
        uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
        uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
        uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
@@ -140,7 +139,6 @@ struct dcn_hubbub_registers {
        uint32_t DCHVM_CLK_CTRL;
        uint32_t DCHVM_RIOMMU_CTRL0;
        uint32_t DCHVM_RIOMMU_STAT0;
-#endif
 };
 
 /* set field name */
@@ -232,7 +230,6 @@ struct dcn_hubbub_registers {
                type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
                type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define HUBBUB_HVM_REG_FIELD_LIST(type) \
                type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
                type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
@@ -278,22 +275,17 @@ struct dcn_hubbub_registers {
                type HOSTVM_POWERSTATUS; \
                type RIOMMU_ACTIVE; \
                type HOSTVM_PREFETCH_DONE
-#endif
 
 struct dcn_hubbub_shift {
        DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
        HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
-#endif
 };
 
 struct dcn_hubbub_mask {
        DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
        HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
-#endif
 };
 
 struct dc;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index fc07538..adba767 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -677,10 +677,8 @@ static void dcn10_bios_golden_init(struct dc *dc)
        int i;
        bool allow_self_fresh_force_enable = true;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
                return;
-#endif
        if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
                allow_self_fresh_force_enable =
                                dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index d5c8615..8c04a36 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -148,7 +148,6 @@
        uint32_t VMID_SETTINGS_0
 
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
        DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
        uint32_t FLIP_PARAMETERS_3;\
@@ -157,7 +156,6 @@
        uint32_t FLIP_PARAMETERS_6;\
        uint32_t VBLANK_PARAMETERS_5;\
        uint32_t VBLANK_PARAMETERS_6
-#endif
 
 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
        DCN_HUBP_REG_FIELD_BASE_LIST(type); \
@@ -184,7 +182,6 @@
        type SURFACE_TRIPLE_BUFFER_ENABLE;\
        type VMID
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
        DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
        type REFCYC_PER_VM_GROUP_FLIP;\
@@ -194,31 +191,18 @@
        type REFCYC_PER_PTE_GROUP_FLIP_C; \
        type REFCYC_PER_META_CHUNK_FLIP_C; \
        type VM_GROUP_SIZE
-#endif
 
 
 struct dcn_hubp2_registers {
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
-#else
-       DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
-#endif
 };
 
 struct dcn_hubp2_shift {
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
-#else
-       DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
-#endif
 };
 
 struct dcn_hubp2_mask {
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
-#else
-       DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
-#endif
 };
 
 struct dcn20_hubp {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d246d94..3d5a79f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2599,11 +2599,9 @@ static void dcn20_calculate_wm(
        context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#endif
 
        if (vlevel < 2) {
                pipes[0].clks_cfg.voltage = 2;
@@ -2615,10 +2613,8 @@ static void dcn20_calculate_wm(
        context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#endif
 
        if (vlevel < 3) {
                pipes[0].clks_cfg.voltage = 3;
@@ -2630,10 +2626,8 @@ static void dcn20_calculate_wm(
        context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#endif
 
        pipes[0].clks_cfg.voltage = vlevel;
        pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
@@ -2643,10 +2637,8 @@ static void dcn20_calculate_wm(
        context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
        context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-#endif
 }
 
 void dcn20_calculate_dlg_params(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 0f6e2a0..39321b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -976,11 +976,9 @@ static void calculate_wm_set_for_vlevel(
        wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
        wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
        wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
        wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
        wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
-#endif
        dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
 
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index dc9dbbc..ae608c3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -42,9 +42,7 @@ enum pp_smu_ver {
        PP_SMU_UNSUPPORTED,
        PP_SMU_VER_RV,
        PP_SMU_VER_NV,
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        PP_SMU_VER_RN,
-#endif
 
        PP_SMU_VER_MAX
 };
@@ -288,9 +286,7 @@ struct pp_smu_funcs {
        union {
                struct pp_smu_funcs_rv rv_funcs;
                struct pp_smu_funcs_nv nv_funcs;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
                struct pp_smu_funcs_rn rn_funcs;
-#endif
 
        };
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index be9815b..6ec923a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -44,8 +44,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
-endif
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
 endif
@@ -59,8 +57,6 @@ DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
 ifdef CONFIG_DRM_AMD_DC_DCN1_0
 DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
-endif
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
 endif
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 9c6016e..2689401 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -29,10 +29,8 @@
 #include "dcn20/display_rq_dlg_calc_20.h"
 #include "dcn20/display_mode_vba_20v2.h"
 #include "dcn20/display_rq_dlg_calc_20v2.h"
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 #include "dcn21/display_mode_vba_21.h"
 #include "dcn21/display_rq_dlg_calc_21.h"
-#endif
 
 const struct dml_funcs dml20_funcs = {
        .validate = dml20_ModeSupportAndSystemConfigurationFull,
@@ -48,14 +46,12 @@ const struct dml_funcs dml20v2_funcs = {
        .rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
 };
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 const struct dml_funcs dml21_funcs = {
         .validate = dml21_ModeSupportAndSystemConfigurationFull,
         .recalculate = dml21_recalculate,
         .rq_dlg_get_dlg_reg = dml21_rq_dlg_get_dlg_reg,
         .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg
 };
-#endif
 
 void dml_init_instance(struct display_mode_lib *lib,
                const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
@@ -72,11 +68,9 @@ void dml_init_instance(struct display_mode_lib *lib,
        case DML_PROJECT_NAVI10v2:
                lib->funcs = dml20v2_funcs;
                break;
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
         case DML_PROJECT_DCN21:
                 lib->funcs = dml21_funcs;
                 break;
-#endif
 
        default:
                break;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 212188b..cf2758c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -34,9 +34,7 @@ enum dml_project {
        DML_PROJECT_RAVEN1,
        DML_PROJECT_NAVI10,
        DML_PROJECT_NAVI10v2,
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
        DML_PROJECT_DCN21,
-#endif
 };
 
 struct display_mode_lib;

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 7791cd2..013cfac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -76,9 +76,10 @@ GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o
 AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20)
-endif
 
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
+###############################################################################
+# DCN 21
+###############################################################################
 GPIO_DCN21 = hw_translate_dcn21.o hw_factory_dcn21.o
 
 AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21))

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
index 2443f9e..4949e0c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
@@ -22,7 +22,6 @@
  * Authors: AMD
  *
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #ifndef __DAL_HW_FACTORY_DCN21_H__
 #define __DAL_HW_FACTORY_DCN21_H__
 
@@ -30,4 +29,3 @@
 void dal_hw_factory_dcn21_init(struct hw_factory *factory);
 
 #endif /* __DAL_HW_FACTORY_DCN20_H__ */
-#endif

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
index 2bfaac2..9462b0a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
@@ -22,7 +22,6 @@
  * Authors: AMD
  *
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #ifndef __DAL_HW_TRANSLATE_DCN21_H__
 #define __DAL_HW_TRANSLATE_DCN21_H__
 
@@ -32,4 +31,3 @@ struct hw_translate;
 void dal_hw_translate_dcn21_init(struct hw_translate *tr);
 
 #endif /* __DAL_HW_TRANSLATE_DCN21_H__ */
-#endif

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index edd7029..fb2d667 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -49,9 +49,7 @@
 #include "dcn10/hw_factory_dcn10.h"
 #endif
 #include "dcn20/hw_factory_dcn20.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #include "dcn21/hw_factory_dcn21.h"
-#endif
 
 #include "diagnostics/hw_factory_diag.h"
 
@@ -97,12 +95,10 @@ bool dal_hw_factory_init(
        case DCN_VERSION_2_0:
                dal_hw_factory_dcn20_init(factory);
                return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case DCN_VERSION_2_1:
                dal_hw_factory_dcn21_init(factory);
                return true;
 #endif
-#endif
 
        default:
                ASSERT_CRITICAL(false);

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 8e10bff..55acfda 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -47,9 +47,7 @@
 #include "dcn10/hw_translate_dcn10.h"
 #endif
 #include "dcn20/hw_translate_dcn20.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #include "dcn21/hw_translate_dcn21.h"
-#endif
 
 #include "diagnostics/hw_translate_diag.h"
 
@@ -92,12 +90,10 @@ bool dal_hw_translate_init(
        case DCN_VERSION_2_0:
                dal_hw_translate_dcn20_init(translate);
                return true;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        case DCN_VERSION_2_1:
                dal_hw_translate_dcn21_init(translate);
                return true;
 #endif
-#endif
 
        default:
                BREAK_TO_DEBUGGER();

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 4e00c26..c98d887 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -87,9 +87,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 struct resource_pool;
 struct dc_state;
 struct resource_context;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 struct clk_bw_params;
-#endif
 
 struct resource_funcs {
        void (*destroy)(struct resource_pool **pool);
@@ -143,11 +141,9 @@ struct resource_funcs {
                        struct dc_state *context,
                        display_e2e_pipe_params_st *pipes,
                        int pipe_cnt);
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        void (*update_bw_bounding_box)(
                        struct dc *dc,
                        struct clk_bw_params *bw_params);
-#endif
 
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 4e18e77..f55203e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -31,7 +31,6 @@
 #define DCN_MINIMUM_DISPCLK_Khz 100000
 #define DCN_MINIMUM_DPPCLK_Khz 100000
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 /* Constants */
 #define DDR4_DRAM_WIDTH   64
 #define WM_A 0
@@ -39,12 +38,10 @@
 #define WM_C 2
 #define WM_D 3
 #define WM_SET_COUNT 4
-#endif
 
 #define DCN_MINIMUM_DISPCLK_Khz 100000
 #define DCN_MINIMUM_DPPCLK_Khz 100000
 
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 /* Will these bw structures be ASIC specific? */
 
 #define MAX_NUM_DPM_LVL                8
@@ -152,7 +149,6 @@ struct clk_bw_params {
        struct clk_limit_table clk_table;
        struct wm_table wm_table;
 };
-#endif
 /* Public interfaces */
 
 struct clk_states {
@@ -193,9 +189,7 @@ struct clk_mgr {
        bool psr_allow_active_cache;
        int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
        int dentist_vco_freq_khz;
-#ifdef CONFIG_DRM_AMD_DC_DCN2_1
        struct clk_bw_params *bw_params;
-#endif
 };
 
 /* forward declarations */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 67b610d..2e2310f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -40,11 +40,9 @@ struct cstate_pstate_watermarks_st {
 struct dcn_watermarks {
        uint32_t pte_meta_urgent_ns;
        uint32_t urgent_ns;
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        uint32_t frac_urg_bw_nom;
        uint32_t frac_urg_bw_flip;
        int32_t urgent_latency_ns;
-#endif
        struct cstate_pstate_watermarks_st cstate_pstate;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 23e3a54..663fa18 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -337,9 +337,7 @@ struct hw_sequencer_funcs {
                        enum dc_clock_type clock_type,
                        struct dc_clock_config *clock_cfg);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        bool (*s0i3_golden_init_wa)(struct dc *dc);
-#endif
 };
 
 void color_space_to_black_color(

diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 75db396..c26300c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -74,11 +74,9 @@ IRQ_DCN2 = irq_service_dcn20.o
 AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN2)
-endif
 ###############################################################################
 # DCN 21
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN2_1
 IRQ_DCN21 = irq_service_dcn21.o
 
 AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 70dbf64..6f56208 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -163,11 +163,9 @@ enum {
 #define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI12_P_A0)
 #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
 #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 #define RENOIR_A0 0x91
 #define DEVICE_ID_RENOIR_1636 0x1636   // Renoir
 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF))
-#endif
 
 /*
  * ASIC chip ID

diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 2db5d4f..0b68591 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -47,9 +47,7 @@ enum dce_version {
        DCN_VERSION_1_0,
        DCN_VERSION_1_01,
        DCN_VERSION_2_0,
-#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
        DCN_VERSION_2_1,
-#endif
        DCN_VERSION_MAX
 };