ARM: shmobile: r8a7790: Add clock index macros for DT sources
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Wed, 11 Dec 2013 14:05:12 +0000 (15:05 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Thu, 19 Dec 2013 07:14:05 +0000 (16:14 +0900)
Add macros usable by device tree sources to reference r8a7790 clocks by
index.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
include/dt-bindings/clock/r8a7790-clock.h [new file with mode: 0644]

diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644 (file)
index 0000000..420f0b0
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN               0
+#define R8A7790_CLK_PLL0               1
+#define R8A7790_CLK_PLL1               2
+#define R8A7790_CLK_PLL3               3
+#define R8A7790_CLK_LB                 4
+#define R8A7790_CLK_QSPI               5
+#define R8A7790_CLK_SDH                        6
+#define R8A7790_CLK_SD0                        7
+#define R8A7790_CLK_SD1                        8
+#define R8A7790_CLK_Z                  9
+
+/* MSTP1 */
+#define R8A7790_CLK_TMU1               11
+#define R8A7790_CLK_TMU3               21
+#define R8A7790_CLK_TMU2               22
+#define R8A7790_CLK_CMT0               24
+#define R8A7790_CLK_TMU0               25
+#define R8A7790_CLK_VSP1_DU1           27
+#define R8A7790_CLK_VSP1_DU0           28
+#define R8A7790_CLK_VSP1_RT            30
+#define R8A7790_CLK_VSP1_SY            31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2             2
+#define R8A7790_CLK_SCIFA1             3
+#define R8A7790_CLK_SCIFA0             4
+#define R8A7790_CLK_SCIFB0             6
+#define R8A7790_CLK_SCIFB1             7
+#define R8A7790_CLK_SCIFB2             16
+#define R8A7790_CLK_SYS_DMAC0          18
+#define R8A7790_CLK_SYS_DMAC1          19
+
+/* MSTP3 */
+#define R8A7790_CLK_TPU0               4
+#define R8A7790_CLK_MMCIF1             5
+#define R8A7790_CLK_SDHI3              11
+#define R8A7790_CLK_SDHI2              12
+#define R8A7790_CLK_SDHI1              13
+#define R8A7790_CLK_SDHI0              14
+#define R8A7790_CLK_MMCIF0             15
+#define R8A7790_CLK_SSUSB              28
+#define R8A7790_CLK_CMT1               29
+#define R8A7790_CLK_USBDMAC0           30
+#define R8A7790_CLK_USBDMAC1           31
+
+/* MSTP5 */
+#define R8A7790_CLK_THERMAL            22
+#define R8A7790_CLK_PWM                        23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI               3
+#define R8A7790_CLK_HSUSB              4
+#define R8A7790_CLK_HSCIF1             16
+#define R8A7790_CLK_HSCIF0             17
+#define R8A7790_CLK_SCIF1              20
+#define R8A7790_CLK_SCIF0              21
+#define R8A7790_CLK_DU2                        22
+#define R8A7790_CLK_DU1                        23
+#define R8A7790_CLK_DU0                        24
+#define R8A7790_CLK_LVDS1              25
+#define R8A7790_CLK_LVDS0              26
+
+/* MSTP8 */
+#define R8A7790_CLK_VIN3               8
+#define R8A7790_CLK_VIN2               9
+#define R8A7790_CLK_VIN1               10
+#define R8A7790_CLK_VIN0               11
+#define R8A7790_CLK_ETHER              13
+#define R8A7790_CLK_SATA1              14
+#define R8A7790_CLK_SATA0              15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5              7
+#define R8A7790_CLK_GPIO4              8
+#define R8A7790_CLK_GPIO3              9
+#define R8A7790_CLK_GPIO2              10
+#define R8A7790_CLK_GPIO1              11
+#define R8A7790_CLK_GPIO0              12
+#define R8A7790_CLK_RCAN1              15
+#define R8A7790_CLK_RCAN0              16
+#define R8A7790_CLK_IICDVFS            26
+#define R8A7790_CLK_I2C3               28
+#define R8A7790_CLK_I2C2               29
+#define R8A7790_CLK_I2C1               30
+#define R8A7790_CLK_I2C0               31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */