arm64: dts: allwinner: a64: enable DVFS
authorVasily Khoruzhick <anarsoul@gmail.com>
Wed, 8 Jan 2020 04:20:18 +0000 (20:20 -0800)
committerMaxime Ripard <maxime@cerno.tech>
Mon, 13 Jan 2020 08:54:53 +0000 (16:54 +0800)
Add CPU regulator and operating points for all the A64-based boards
that are currently supported to enable DVFS.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts

index ac979de..c7bd73f 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &csi {
        status = "okay";
 
index 2e00c44..883f217 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index e7b64a5..e58db8a 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
        status = "okay";
 };
index d387d74..c52cf7e 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
        status = "okay";
 };
index 72120e4..fde9c7a 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index 6f817cf..2165f23 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index b47147e..3d894b2 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/gpio-keys.h>
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index f1204fc..c48692b 100644 (file)
@@ -4,6 +4,7 @@
 //   Copyright (c) 2016 ARM Ltd.
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
        cpvdd-supply = <&reg_eldo1>;
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins>;
index 421454c..f5df5f7 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &ehci1 {
        status = "okay";
 };