net/mlx5: Fix size field in bufferx_reg struct
authorMohammad Kabat <mohammadkab@nvidia.com>
Thu, 25 Mar 2021 12:38:55 +0000 (14:38 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 9 Mar 2022 19:39:34 +0000 (11:39 -0800)
According to HW spec the field "size" should be 16 bits
in bufferx register.

Fixes: e281682bf294 ("net/mlx5_core: HW data structs/types definitions cleanup")
Signed-off-by: Mohammad Kabat <mohammadkab@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
include/linux/mlx5/mlx5_ifc.h

index 598ac3b..5743f5b 100644 (file)
@@ -9900,8 +9900,8 @@ struct mlx5_ifc_bufferx_reg_bits {
        u8         reserved_at_0[0x6];
        u8         lossy[0x1];
        u8         epsb[0x1];
-       u8         reserved_at_8[0xc];
-       u8         size[0xc];
+       u8         reserved_at_8[0x8];
+       u8         size[0x10];
 
        u8         xoff_threshold[0x10];
        u8         xon_threshold[0x10];