Merge git://git.denx.de/u-boot-socfpga

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 9650eb0..5465609 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -69,6 +69,9 @@
 };
 
 &mmc0 {
+       status = "okay";
+       u-boot,dm-pre-reloc;
+
        cd-gpios = <&portb 18 0>;
        vmmc-supply = <&regulator_3_3v>;
        vqmmc-supply = <&regulator_3_3v>;

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index de7650e..d588f94 100644 (file)
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -17,6 +17,8 @@
 #define L2X0_CTRL_EN                           1
 
 #define L310_SHARED_ATT_OVERRIDE_ENABLE                (1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK       (1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK       (1 << 29)
 
 struct pl310_regs {
        u32 pl310_cache_id;

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 0940cc5..bbd31ef 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -52,6 +52,18 @@ void enable_caches(void)
 #endif
 }
 
+void v7_outer_cache_enable(void)
+{
+       /* disable the L2 cache */
+       writel(0, &pl310->pl310_ctrl);
+
+       /* enable BRESP, instruction and data prefetch, full line of zeroes */
+       setbits_le32(&pl310->pl310_aux_ctrl,
+                    L310_AUX_CTRL_DATA_PREFETCH_MASK |
+                    L310_AUX_CTRL_INST_PREFETCH_MASK |
+                    L310_SHARED_ATT_OVERRIDE_ENABLE);
+}
+
 /*
  * DesignWare Ethernet initialization
  */