gas/testsuite/

2009-04-15  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/x86-64-sse5.s: Add test of protd.
	* gas/i386/x86-64-sse5.d: Adjust expectations to match input.

opcodes/
2009-04-15  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl (protb, protw, protd, protq): Set opcode
	extension to None.
	(pshab, pshaw, pshad, pshaq): Likewise.
	* i386-tbl.h: Re-generate.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 4e0d44f..8da6574 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-04-15  Jan Beulich  <jbeulich@novell.com>
+
+       * gas/i386/x86-64-sse5.s: Add test of protd.
+       * gas/i386/x86-64-sse5.d: Adjust expectations to match input.
+
 2009-04-09  Catherine Moore  <clm@codesourcery.com>
 
        * gas/mips/mips.exp: Run new tests.

diff --git a/gas/testsuite/gas/i386/x86-64-sse5.d b/gas/testsuite/gas/i386/x86-64-sse5.d
index 92b1c90..a6d492d 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse5.d
+++ b/gas/testsuite/gas/i386/x86-64-sse5.d
@@ -2838,7 +2838,8 @@ Disassembly of section .text:
 [      ]+48c8:[        ]+41 0f 7a 30 8f 00 00 10 00[   ]+cvtph2ps 0x100000\(%r15\),%xmm1
 [      ]+48d1:[        ]+0f 7a 31 d1[  ]+cvtps2ph %xmm2,%xmm1
 [      ]+48d5:[        ]+41 0f 7a 31 8f 00 00 10 00[   ]+cvtps2ph %xmm1,0x100000\(%r15\)
-[      ]+48de:[        ]+0f 7b 40 41 04 04[    ]+protb[        ]+\$0x4,0x4\(%rcx\),%xmm0
-[      ]+48e4:[        ]+41 0f 7b 41 42 08 01[         ]+protw[        ]+\$0x1,0x8\(%r10\),%xmm0
-[      ]+48eb:[        ]+41 0f 7b 43 41 04 03[         ]+protq[        ]+\$0x3,0x4\(%r9\),%xmm0
-[      ]+48f2:[        ]+c3[   ]+retq[         ]*
+[      ]+48de:[        ]+0f 7b 40 4a 04 04[    ]+protb[        ]+\$0x4,0x4\(%rdx\),%xmm1
+[      ]+48e4:[        ]+41 0f 7b 41 56 08 01[         ]+protw[        ]+\$0x1,0x8\(%r14\),%xmm2
+[      ]+48eb:[        ]+44 0f 7b 42 b8 00 00 01 00 02[        ]+protd[        ]+\$0x2,0x10000\(%rax\),%xmm15
+[      ]+48f5:[        ]+41 0f 7b 43 4f 04 03[         ]+protq[        ]+\$0x3,0x4\(%r15\),%xmm1
+[      ]+48fc:[        ]+c3[   ]+retq[         ]*

diff --git a/gas/testsuite/gas/i386/x86-64-sse5.s b/gas/testsuite/gas/i386/x86-64-sse5.s
index 0926e45..4dd7d2c 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse5.s
+++ b/gas/testsuite/gas/i386/x86-64-sse5.s
@@ -2968,6 +2968,7 @@ foo:
 
        protb           $0x4, 0x4(%rdx), %xmm1
        protw           $0x1, 0x8(%r14), %xmm2
+       protd           $0x2, 0x10000(%rax), %xmm15
        protq           $0x3, 0x4(%r15), %xmm1
        
        ret

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 37c14fc..a8f748e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2009-04-15  Jan Beulich  <jbeulich@novell.com>
+
+       * i386-opc.tbl (protb, protw, protd, protq): Set opcode
+       extension to None.
+       (pshab, pshaw, pshad, pshaq): Likewise.
+       * i386-tbl.h: Re-generate.
+
 2009-04-07  Peter Bergner  <bergner@vnet.ibm.com>
 
        * ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index edd1fde..ec64496 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2588,21 +2588,21 @@ pperm, 4, 0x0f2423, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|N
 permps, 4, 0x0f2420, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 permpd, 4, 0x0f2421, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protb, 3, 0x0f2440, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protb, 3, 0x0f7b40, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protw, 3, 0x0f2441, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protw, 3, 0x0f7b41, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protd, 3, 0x0f2442, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protd, 3, 0x0f7b42, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protq, 3, 0x0f2443, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+protq, 3, 0x0f7b43, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlb, 3, 0x0f2444, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlw, 3, 0x0f2445, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshld, 3, 0x0f2446, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlq, 3, 0x0f2447, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshab, 3, 0x0f2448, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshaw, 3, 0x0f2449, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshad, 3, 0x0f244a, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-pshaq, 3, 0x0f244b, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshab, 3, 0x0f2448, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshaw, 3, 0x0f2449, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshad, 3, 0x0f244a, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
+pshaq, 3, 0x0f244b, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 comps, 4, 0x0f252c, 0x0, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|Drexc,      { Imm8,            Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }
 comeqps, 3, 0x0f252c, 0x0, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|ImmExt|Drexc,      { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }
 comltps, 3, 0x0f252c, 0x1, 3, CpuSSE5, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Modrm|ImmExt|Drexc,      { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM,          RegXMM }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 232d10b..c90b154 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -27866,7 +27866,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "protb", 3, 0x0f7b40, 0x0, 3,
+  { "protb", 3, 0x0f7b40, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -27896,7 +27896,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "protw", 3, 0x0f7b41, 0x0, 3,
+  { "protw", 3, 0x0f7b41, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -27926,7 +27926,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "protd", 3, 0x0f7b42, 0x0, 3,
+  { "protd", 3, 0x0f7b42, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -27956,7 +27956,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "protq", 3, 0x0f7b43, 0x0, 3,
+  { "protq", 3, 0x0f7b43, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -28031,7 +28031,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "pshab", 3, 0x0f2448, 0x0, 3,
+  { "pshab", 3, 0x0f2448, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -28046,7 +28046,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "pshaw", 3, 0x0f2449, 0x0, 3,
+  { "pshaw", 3, 0x0f2449, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -28061,7 +28061,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "pshad", 3, 0x0f244a, 0x0, 3,
+  { "pshad", 3, 0x0f244a, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 
@@ -28076,7 +28076,7 @@ const template i386_optab[] =
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
          0, 0, 0, 0, 0 } } } },
-  { "pshaq", 3, 0x0f244b, 0x0, 3,
+  { "pshaq", 3, 0x0f244b, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,