[InstCombine] add test for miscompile in dropRedundantMaskingOfLeftShiftInput();...

diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
index aa644e6..3718ff4 100644 (file)
--- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
+++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
@@ -245,3 +245,24 @@ define i32 @n6_extrause2(i64 %x, i32 %nbits) {
   %t6 = shl i32 %t5, %t3 ; shift is smaller than mask
   ret i32 %t6
 }
+
+; FIXME:
+; This is a miscompile if it ends by masking off the high bit of the result.
+
+define i32 @PR51351(i64 %x, i32 %nbits) {
+; CHECK-LABEL: @PR51351(
+; CHECK-NEXT:    [[T3:%.*]] = add i32 [[NBITS:%.*]], -33
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
+; CHECK-NEXT:    [[TMP2:%.*]] = shl i32 [[TMP1]], [[T3]]
+; CHECK-NEXT:    [[T6:%.*]] = and i32 [[TMP2]], 2147483647
+; CHECK-NEXT:    ret i32 [[T6]]
+;
+  %t0 = zext i32 %nbits to i64
+  %t1 = shl i64 -1, %t0
+  %t2 = ashr i64 %t1, %t0
+  %t3 = add i32 %nbits, 4294967263
+  %t4 = and i64 %t2, %x
+  %t5 = trunc i64 %t4 to i32
+  %t6 = shl i32 %t5, %t3
+  ret i32 %t6
+}