bus: mhi: pci_generic: Introduce quectel EM1XXGR-L support

Add support for EM1XXGR-L modems, this modem series is based on SDX24
qcom chip. The modem is mainly based on MBIM protocol for both the
data and control path. The drivers for these channels (mhi-net-mbim and
mhi_uci) are not yet part of the kernel but will be integrated by
different series.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/1614971808-22156-2-git-send-email-loic.poulain@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
index 68c1c86..2751503 100644 (file)
--- a/drivers/bus/mhi/pci_generic.c
+++ b/drivers/bus/mhi/pci_generic.c
@@ -114,6 +114,36 @@ struct mhi_pci_dev_info {
                .doorbell_mode_switch = true,           \
        }
 
+#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
+       {                                               \
+               .num = ch_num,                          \
+               .name = ch_name,                        \
+               .num_elements = el_count,               \
+               .event_ring = ev_ring,                  \
+               .dir = DMA_TO_DEVICE,                   \
+               .ee_mask = BIT(MHI_EE_SBL),             \
+               .pollcfg = 0,                           \
+               .doorbell = MHI_DB_BRST_DISABLE,        \
+               .lpm_notify = false,                    \
+               .offload_channel = false,               \
+               .doorbell_mode_switch = false,          \
+       }                                               \
+
+#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
+       {                                               \
+               .num = ch_num,                          \
+               .name = ch_name,                        \
+               .num_elements = el_count,               \
+               .event_ring = ev_ring,                  \
+               .dir = DMA_FROM_DEVICE,                 \
+               .ee_mask = BIT(MHI_EE_SBL),             \
+               .pollcfg = 0,                           \
+               .doorbell = MHI_DB_BRST_DISABLE,        \
+               .lpm_notify = false,                    \
+               .offload_channel = false,               \
+               .doorbell_mode_switch = false,          \
+       }
+
 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
        {                                       \
                .num_elements = el_count,       \
@@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
        .dma_data_width = 32
 };
 
+static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
+       MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
+       MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
+       MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
+       MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
+       MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
+       MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
+       MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
+       MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
+       MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
+       MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
+       MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
+       MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
+};
+
+static struct mhi_event_config mhi_quectel_em1xx_events[] = {
+       MHI_EVENT_CONFIG_CTRL(0, 128),
+       MHI_EVENT_CONFIG_DATA(1, 128),
+       MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
+       MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
+};
+
+static struct mhi_controller_config modem_quectel_em1xx_config = {
+       .max_channels = 128,
+       .timeout_ms = 20000,
+       .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
+       .ch_cfg = mhi_quectel_em1xx_channels,
+       .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
+       .event_cfg = mhi_quectel_em1xx_events,
+};
+
+static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
+       .name = "quectel-em1xx",
+       .edl = "qcom/prog_firehose_sdx24.mbn",
+       .config = &modem_quectel_em1xx_config,
+       .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
+       .dma_data_width = 32
+};
+
 static const struct pci_device_id mhi_pci_id_table[] = {
        { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
                .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
+       { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
+               .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+       { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
+               .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
        {  }
 };
 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);