drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW

On HSW the pipe colorspace is configured via PIPECONF
(as opposed to PIPEMISC in BDW+). Let's configure+readout
that stuff correctly.

Enabling YCbCr 4:4:4 output will now be a simple matter of
setting crtc_state->output_format appropriately in the encoder
.compute_config().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-10-ville.syrjala@linux.intel.com
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 95a63ac..1bd91a0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9444,6 +9444,10 @@ static void haswell_set_pipeconf(const struct intel_crtc_state *crtc_state)
        else
                val |= PIPECONF_PROGRESSIVE;
 
+       if (IS_HASWELL(dev_priv) &&
+           crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+               val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
+
        I915_WRITE(PIPECONF(cpu_transcoder), val);
        POSTING_READ(PIPECONF(cpu_transcoder));
 }
@@ -10440,7 +10444,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
        intel_get_pipe_src_size(crtc, pipe_config);
 
-       if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+       if (IS_HASWELL(dev_priv)) {
+               u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
+
+               if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
+                       pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
+               else
+                       pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+       } else {
                pipe_config->output_format =
                        bdw_get_pipemisc_output_format(crtc);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3cc1baa..6f2eda7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5683,6 +5683,7 @@ enum {
 #define   PIPECONF_CXSR_DOWNCLOCK      (1 << 16)
 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV      (1 << 14)
 #define   PIPECONF_COLOR_RANGE_SELECT  (1 << 13)
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW   (1 << 11) /* hsw only */
 #define   PIPECONF_BPC_MASK    (0x7 << 5)
 #define   PIPECONF_8BPC                (0 << 5)
 #define   PIPECONF_10BPC       (1 << 5)