xtensa: xtfpga: fix serial port register width and endianness

Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index cd0b9e3..be3fd76 100644 (file)
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -60,6 +60,8 @@
                        no-loopback-test;
                        reg = <0x0d050020 0x20>;
                        reg-shift = <2>;
+                       reg-io-width = <4>;
+                       native-endian;
                        interrupts = <0 1>; /* external irq 0 */
                        clocks = <&osc>;
                };

diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index e9f65f7..b7f468a 100644 (file)
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -283,7 +283,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                .irq            = DUART16552_INTNUM,
                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
                                  UPF_IOREMAP,
-               .iotype         = UPIO_MEM32,
+               .iotype         = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
                .regshift       = 2,
                .uartclk        = 0,    /* set in xtavnet_init() */
        },