ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
authorChen-Yu Tsai <wens@csie.org>
Tue, 10 Mar 2020 17:47:08 +0000 (01:47 +0800)
committerChen-Yu Tsai <wens@csie.org>
Wed, 11 Mar 2020 14:47:58 +0000 (22:47 +0800)
When the SPI device nodes were added, SPI2 and SPI3 had incorrect
register base addresses.

Fix the base address for both of them.

Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Reported-by: JuanEsf <juanesf91@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
arch/arm/boot/dts/sun8i-r40.dtsi

index bb606ea..43c9239 100644 (file)
                        #size-cells = <0>;
                };
 
-               spi2: spi@1c07000 {
+               spi2: spi@1c17000 {
                        compatible = "allwinner,sun8i-r40-spi",
                                     "allwinner,sun8i-h3-spi";
-                       reg = <0x01c07000 0x1000>;
+                       reg = <0x01c17000 0x1000>;
                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
                        clock-names = "ahb", "mod";
                        #size-cells = <0>;
                };
 
-               spi3: spi@1c0f000 {
+               spi3: spi@1c1f000 {
                        compatible = "allwinner,sun8i-r40-spi",
                                     "allwinner,sun8i-h3-spi";
-                       reg = <0x01c0f000 0x1000>;
+                       reg = <0x01c1f000 0x1000>;
                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
                        clock-names = "ahb", "mod";