CHIPSET(0x56b1, dg2_g11, "DG2", "Intel(R) Arc(tm) Pro A40/A50 Graphics")
CHIPSET(0x56b2, dg2_g12, "DG2", "Intel(R) Graphics")
CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics")
-CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Data Center GPU Flex Series 170 Graphics")
-CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Data Center GPU Flex Series 140 Graphics")
+CHIPSET(0x56c0, atsm_g10, "ATS-M", "Intel(R) Data Center GPU Flex Series 170 Graphics")
+CHIPSET(0x56c1, atsm_g11, "ATS-M", "Intel(R) Data Center GPU Flex Series 140 Graphics")
CHIPSET(0x7d40, mtl_m, "MTL", "Intel(R) Graphics")
CHIPSET(0x7d45, mtl_p, "MTL", "Intel(R) Graphics")
.platform = INTEL_PLATFORM_DG2_G12,
};
+static const struct intel_device_info intel_device_info_atsm_g10 = {
+ DG2_FEATURES,
+ .platform = INTEL_PLATFORM_ATSM_G10,
+};
+
+static const struct intel_device_info intel_device_info_atsm_g11 = {
+ DG2_FEATURES,
+ .platform = INTEL_PLATFORM_ATSM_G11,
+};
+
#define MTL_FEATURES \
/* (Sub)slice info comes from the kernel topology info */ \
XEHP_FEATURES(0, 1, 0), \
INTEL_PLATFORM_GROUP_START(DG2, INTEL_PLATFORM_DG2_G10),
INTEL_PLATFORM_DG2_G11,
INTEL_PLATFORM_GROUP_END(DG2, INTEL_PLATFORM_DG2_G12),
+ INTEL_PLATFORM_GROUP_START(ATSM, INTEL_PLATFORM_ATSM_G10),
+ INTEL_PLATFORM_GROUP_END(ATSM, INTEL_PLATFORM_ATSM_G11),
INTEL_PLATFORM_GROUP_START(MTL, INTEL_PLATFORM_MTL_M),
INTEL_PLATFORM_GROUP_END(MTL, INTEL_PLATFORM_MTL_P),
};
(((platform) >= INTEL_PLATFORM_ ## platform_range ## _START) && \
((platform) <= INTEL_PLATFORM_ ## platform_range ## _END))
+#define intel_device_info_is_atsm(devinfo) \
+ intel_platform_in_range((devinfo)->platform, ATSM)
+
#define intel_device_info_is_dg2(devinfo) \
- intel_platform_in_range((devinfo)->platform, DG2)
+ (intel_platform_in_range((devinfo)->platform, DG2) || \
+ intel_platform_in_range((devinfo)->platform, ATSM))
#define intel_device_info_is_mtl(devinfo) \
intel_platform_in_range((devinfo)->platform, MTL)