armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce8..17c150a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -98,6 +98,10 @@
 #define DCFG_DCSR_BASE         0X700100000ULL
 #define DCFG_DCSR_PORCR1               0x000
 
+/* Interrupt Sampling Control */
+#define ISC_BASE               0x01F70000
+#define IRQCR_OFFSET           0x14
+
 /* Supplemental Configuration */
 #define SCFG_BASE              0x01fc0000
 #define SCFG_USB3PRM1CR                        0x000

diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index c63b639..12638df 100644 (file)
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -149,6 +149,7 @@ int board_init(void)
 {
        char *env_hwconfig;
        u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+       u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
        u32 val;
 
        init_final_memctl_regs();
@@ -170,6 +171,9 @@ int board_init(void)
 
        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+       /* invert AQR405 IRQ pins polarity */
+       out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+
        return 0;
 }
 

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b2c0181..14635b7 100644 (file)
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -355,6 +355,7 @@ unsigned long get_board_sys_clk(void);
 #define AQ_PHY_ADDR2           0x01
 #define AQ_PHY_ADDR3           0x02
 #define AQ_PHY_ADDR4           0x03
+#define AQR405_IRQ_MASK                0x36
 
 #define CONFIG_MII
 #define CONFIG_ETHPRIME                "DPNI1"