drm/nv04/disp: handle dual-link spwg panels without needing quirks
authorBen Skeggs <bskeggs@redhat.com>
Fri, 18 Nov 2011 01:55:43 +0000 (11:55 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 21 Dec 2011 09:01:43 +0000 (19:01 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/nouveau/nv04_dfp.c

index 1faa7d9..f8df372 100644 (file)
@@ -4304,18 +4304,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
                break;
        }
 
-       /* Dell Latitude D620 reports a too-high value for the dual-link
-        * transition freq, causing us to program the panel incorrectly.
-        *
-        * It doesn't appear the VBIOS actually uses its transition freq
-        * (90000kHz), instead it uses the "Number of LVDS channels" field
-        * out of the panel ID structure (http://www.spwg.org/).
-        *
-        * For the moment, a quirk will do :)
-        */
-       if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
-               bios->fp.duallink_transition_clk = 80000;
-
        /* set dual_link flag for EDID case */
        if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
                bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
index dff3ad5..2258746 100644 (file)
@@ -341,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
            output_mode->clock > 165000)
                regp->fp_control |= (2 << 24);
        if (nv_encoder->dcb->type == OUTPUT_LVDS) {
-               bool duallink, dummy;
+               bool duallink = false, dummy;
+               if (nv_connector->edid &&
+                   nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
+                       duallink = (((u8 *)nv_connector->edid)[121] == 2);
+               } else {
+                       nouveau_bios_parse_lvds_table(dev, output_mode->clock,
+                                                     &duallink, &dummy);
+               }
 
-               nouveau_bios_parse_lvds_table(dev, output_mode->clock,
-                                             &duallink, &dummy);
                if (duallink)
                        regp->fp_control |= (8 << 28);
        } else