/* Make sure device is powered up for SRAM reads */
spin_lock_irqsave(&priv->trans->reg_lock, reg_flags);
- if (unlikely(!iwl_trans_grab_nic_access(priv->trans, false))) {
+ if (!iwl_trans_grab_nic_access(priv->trans, false)) {
spin_unlock_irqrestore(&priv->trans->reg_lock, reg_flags);
return;
}
/* Make sure device is powered up for SRAM reads */
spin_lock_irqsave(&trans->reg_lock, reg_flags);
- if (unlikely(!iwl_trans_grab_nic_access(trans, false)))
+ if (!iwl_trans_grab_nic_access(trans, false))
goto out_unlock;
/* Set starting address; reads will auto-increment */
}
iwl_read32(priv->trans, CSR_UCODE_DRV_GP1);
spin_lock_irqsave(&priv->trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(priv->trans, false)))
+ if (iwl_trans_grab_nic_access(priv->trans, false))
iwl_trans_release_nic_access(priv->trans);
spin_unlock_irqrestore(&priv->trans->reg_lock, flags);
u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
{
- u32 value;
+ u32 value = 0x5a5a5a5a;
unsigned long flags;
spin_lock_irqsave(&trans->reg_lock, flags);
- iwl_trans_grab_nic_access(trans, false);
- value = iwl_read32(trans, reg);
- iwl_trans_release_nic_access(trans);
+ if (iwl_trans_grab_nic_access(trans, false)) {
+ value = iwl_read32(trans, reg);
+ iwl_trans_release_nic_access(trans);
+ }
spin_unlock_irqrestore(&trans->reg_lock, flags);
return value;
unsigned long flags;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
iwl_write32(trans, reg, value);
iwl_trans_release_nic_access(trans);
}
u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
{
unsigned long flags;
- u32 val;
+ u32 val = 0x5a5a5a5a;
spin_lock_irqsave(&trans->reg_lock, flags);
- iwl_trans_grab_nic_access(trans, false);
- val = __iwl_read_prph(trans, ofs);
- iwl_trans_release_nic_access(trans);
+ if (iwl_trans_grab_nic_access(trans, false)) {
+ val = __iwl_read_prph(trans, ofs);
+ iwl_trans_release_nic_access(trans);
+ }
spin_unlock_irqrestore(&trans->reg_lock, flags);
return val;
}
unsigned long flags;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
__iwl_write_prph(trans, ofs, val);
iwl_trans_release_nic_access(trans);
}
unsigned long flags;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
__iwl_write_prph(trans, ofs,
__iwl_read_prph(trans, ofs) | mask);
iwl_trans_release_nic_access(trans);
unsigned long flags;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
__iwl_write_prph(trans, ofs,
(__iwl_read_prph(trans, ofs) & mask) | bits);
iwl_trans_release_nic_access(trans);
u32 val;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
val = __iwl_read_prph(trans, ofs);
__iwl_write_prph(trans, ofs, (val & ~mask));
iwl_trans_release_nic_access(trans);
if (IWL_ABS_PRPH_START <= addr &&
addr < IWL_ABS_PRPH_START + PRPH_END) {
spin_lock_irqsave(&trans->reg_lock, flags);
- iwl_trans_grab_nic_access(trans, false);
+ if (!iwl_trans_grab_nic_access(trans, false)) {
+ spin_unlock_irqrestore(&trans->reg_lock, flags);
+ return -EIO;
+ }
iwl_write32(trans, HBUS_TARG_PRPH_RADDR,
addr | (3 << 24));
for (i = 0; i < size; i += 4)
if (IWL_ABS_PRPH_START <= addr &&
addr < IWL_ABS_PRPH_START + PRPH_END) {
- /* Periphery writes can be 1-3 bytes long, or DWORDs */
- if (size < 4) {
- memcpy(&val, buf, size);
- spin_lock_irqsave(&trans->reg_lock, flags);
- iwl_trans_grab_nic_access(trans, false);
- iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
- (addr & 0x0000FFFF) |
- ((size - 1) << 24));
- iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
- iwl_trans_release_nic_access(trans);
- /* needed after consecutive writes w/o read */
- mmiowb();
+ /* Periphery writes can be 1-3 bytes long, or DWORDs */
+ if (size < 4) {
+ memcpy(&val, buf, size);
+ spin_lock_irqsave(&trans->reg_lock, flags);
+ if (!iwl_trans_grab_nic_access(trans, false)) {
spin_unlock_irqrestore(&trans->reg_lock, flags);
- } else {
- if (size % 4)
- return -EINVAL;
- for (i = 0; i < size; i += 4)
- iwl_write_prph(trans, addr+i,
- *(u32 *)(buf+i));
+ return -EIO;
}
+ iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
+ (addr & 0x0000FFFF) |
+ ((size - 1) << 24));
+ iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
+ iwl_trans_release_nic_access(trans);
+ /* needed after consecutive writes w/o read */
+ mmiowb();
+ spin_unlock_irqrestore(&trans->reg_lock, flags);
+ } else {
+ if (size % 4)
+ return -EINVAL;
+ for (i = 0; i < size; i += 4)
+ iwl_write_prph(trans, addr+i,
+ *(u32 *)(buf+i));
+ }
} else if (iwl_test_valid_hw_addr(tst, addr)) {
iwl_trans_write_mem(trans, addr, buf, size / 4);
} else {
trans->ops->set_pmi(trans, state);
}
-static inline bool iwl_trans_grab_nic_access(struct iwl_trans *trans,
- bool silent)
-{
- return trans->ops->grab_nic_access(trans, silent);
-}
+#define iwl_trans_grab_nic_access(trans, silent) \
+ __cond_lock(nic_access, \
+ likely((trans)->ops->grab_nic_access(trans, silent)))
-static inline void iwl_trans_release_nic_access(struct iwl_trans *trans)
+static inline void __releases(nic_access)
+iwl_trans_release_nic_access(struct iwl_trans *trans)
{
trans->ops->release_nic_access(trans);
+ __release(nic_access);
}
/*****************************************************
u32 *vals = buf;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
for (offs = 0; offs < dwords; offs++)
vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
u32 *vals = buf;
spin_lock_irqsave(&trans->reg_lock, flags);
- if (likely(iwl_trans_grab_nic_access(trans, false))) {
+ if (iwl_trans_grab_nic_access(trans, false)) {
iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
for (offs = 0; offs < dwords; offs++)
iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);