return;
}
+ auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
+ int64_t SExtVal = SignExtend64(Value, RegWidth);
+ O << "\tmov\t";
+ printRegName(O, MI->getOperand(0).getReg());
+ O << ", " << markup("<imm:") << "#"
+ << formatImm(SExtVal) << markup(">");
+ if (CommentStream) {
+ // Do the opposite to that used for instruction operands.
+ if (getPrintImmHex())
+ *CommentStream << '=' << formatDec(SExtVal) << '\n';
+ else {
+ uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
+ *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
+ }
+ }
+ };
+
// MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
// domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
// MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
if (AArch64_AM::isMOVZMovAlias(Value, Shift,
Opcode == AArch64::MOVZXi ? 64 : 32)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
Value = Value & 0xffffffff;
if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
uint64_t Value = AArch64_AM::decodeLogicalImmediate(
MI->getOperand(2).getImm(), RegWidth);
if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
- O << "\tmov\t";
- printRegName(O, MI->getOperand(0).getReg());
- O << ", " << markup("<imm:") << "#"
- << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+ PrintMovImm(Value, RegWidth);
return;
}
}
define i64 @test1() {
; CHECK-LABEL: test1:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: mov w0, #1 ; =0x1
; CHECK-NEXT: ret
ret i64 1
}
define i64 @test2() {
; CHECK-LABEL: test2:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #65535
+; CHECK-NEXT: mov w0, #65535 ; =0xffff
; CHECK-NEXT: ret
ret i64 65535
}
define i64 @test3() {
; CHECK-LABEL: test3:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #65536
+; CHECK-NEXT: mov w0, #65536 ; =0x10000
; CHECK-NEXT: ret
ret i64 65536
}
define i64 @test4() {
; CHECK-LABEL: test4:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #-65536
+; CHECK-NEXT: mov w0, #-65536 ; =0xffff0000
; CHECK-NEXT: ret
ret i64 4294901760
}
define i64 @test5() {
; CHECK-LABEL: test5:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #4294967296
+; CHECK-NEXT: mov x0, #4294967296 ; =0x100000000
; CHECK-NEXT: ret
ret i64 4294967296
}
define i64 @test6() {
; CHECK-LABEL: test6:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #281470681743360
+; CHECK-NEXT: mov x0, #281470681743360 ; =0xffff00000000
; CHECK-NEXT: ret
ret i64 281470681743360
}
define i64 @test7() {
; CHECK-LABEL: test7:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #281474976710656
+; CHECK-NEXT: mov x0, #281474976710656 ; =0x1000000000000
; CHECK-NEXT: ret
ret i64 281474976710656
}
define i64 @test8() {
; CHECK-LABEL: test8:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov w0, #-60876
+; CHECK-NEXT: mov w0, #-60876 ; =0xffff1234
; CHECK-NEXT: ret
ret i64 4294906420
}
define i64 @test9() {
; CHECK-LABEL: test9:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-1
+; CHECK-NEXT: mov x0, #-1 ; =0xffffffffffffffff
; CHECK-NEXT: ret
ret i64 -1
}
define i64 @test10() {
; CHECK-LABEL: test10:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-3989504001
+; CHECK-NEXT: mov x0, #-3989504001 ; =0xffffffff1234ffff
; CHECK-NEXT: ret
ret i64 18446744069720047615
}
; CHECK-LABEL: test12:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
-; CHECK-NEXT: mov w9, #1
+; CHECK-NEXT: mov w9, #1 ; =0x1
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 1, ptr @var32
; CHECK-LABEL: test13:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
-; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: mov w9, #65535 ; =0xffff
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 65535, ptr @var32
; CHECK-LABEL: test14:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
-; CHECK-NEXT: mov w9, #65536
+; CHECK-NEXT: mov w9, #65536 ; =0x10000
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 65536, ptr @var32
; CHECK-LABEL: test15:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
-; CHECK-NEXT: mov w9, #-65536
+; CHECK-NEXT: mov w9, #-65536 ; =0xffff0000
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 4294901760, ptr @var32
; CHECK-LABEL: test16:
; CHECK: ; %bb.0:
; CHECK-NEXT: adrp x8, _var32@PAGE
-; CHECK-NEXT: mov w9, #-1
+; CHECK-NEXT: mov w9, #-1 ; =0xffffffff
; CHECK-NEXT: str w9, [x8, _var32@PAGEOFF]
; CHECK-NEXT: ret
store i32 -1, ptr @var32
define i64 @test17() {
; CHECK-LABEL: test17:
; CHECK: ; %bb.0:
-; CHECK-NEXT: mov x0, #-3
+; CHECK-NEXT: mov x0, #-3 ; =0xfffffffffffffffd
; CHECK-NEXT: ret
; Mustn't MOVN w0 here.
define hidden i32 @"_Z54bar$ompvariant$bar"() {
; LINUX-LABEL: _Z54bar$ompvariant$bar:
; LINUX: // %bb.0: // %entry
-; LINUX-NEXT: mov w0, #2
+; LINUX-NEXT: mov w0, #2 // =0x2
; LINUX-NEXT: ret
;
; DARWIN-LABEL: _Z54bar$ompvariant$bar:
; DARWIN: ; %bb.0: ; %entry
-; DARWIN-NEXT: mov w0, #2
+; DARWIN-NEXT: mov w0, #2 ; =0x2
; DARWIN-NEXT: ret
entry:
ret i32 2
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: stur xzr, [x29, #-8]
; CHECK-NEXT: cbz wzr, .LBB0_3
; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: ldur w8, [x29, #-8]
; CHECK-NEXT: cbz w8, .LBB0_4
; CHECK-NEXT: .LBB0_2:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: str w8, [sp, #16]
; CHECK-NEXT: b .LBB0_5
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: ldur w8, [x29, #-8]
; CHECK-NEXT: cbnz w8, .LBB0_2
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: adrp x9, x
-; CHECK-NEXT: mov w10, #2
-; CHECK-NEXT: mov w11, #3
+; CHECK-NEXT: mov w10, #2 // =0x2
+; CHECK-NEXT: mov w11, #3 // =0x3
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: str w8, [x9, :lo12:x]
-; CHECK-NEXT: mov w9, #4
+; CHECK-NEXT: mov w9, #4 // =0x4
; CHECK-NEXT: stp w8, wzr, [x29, #-8]
; CHECK-NEXT: stur w10, [x29, #-12]
; CHECK-NEXT: stp w9, w11, [sp, #12]
;
; CHECK-LABEL: OUTLINED_FUNCTION_0:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #2
-; CHECK-NEXT: mov w10, #3
-; CHECK-NEXT: mov w11, #4
+; CHECK-NEXT: mov w9, #2 // =0x2
+; CHECK-NEXT: mov w10, #3 // =0x3
+; CHECK-NEXT: mov w11, #4 // =0x4
; CHECK-NEXT: stp w9, w8, [x29, #-12]
; CHECK-NEXT: stp w11, w10, [sp, #12]
; CHECK-NEXT: ret
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: stur xzr, [x29, #-8]
; CHECK-NEXT: cbz wzr, .LBB0_3
; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: ldur w8, [x29, #-8]
; CHECK-NEXT: cbz w8, .LBB0_4
; CHECK-NEXT: .LBB0_2:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: str w8, [sp, #16]
; CHECK-NEXT: b .LBB0_5
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: ldur w8, [x29, #-8]
; CHECK-NEXT: cbnz w8, .LBB0_2
; CHECK-NEXT: .LBB0_4:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: bl OUTLINED_FUNCTION_0
; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: adrp x9, x
-; CHECK-NEXT: mov w10, #2
-; CHECK-NEXT: mov w11, #3
+; CHECK-NEXT: mov w10, #2 // =0x2
+; CHECK-NEXT: mov w11, #3 // =0x3
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: str w8, [x9, :lo12:x]
-; CHECK-NEXT: mov w9, #4
+; CHECK-NEXT: mov w9, #4 // =0x4
; CHECK-NEXT: stp w8, wzr, [x29, #-8]
; CHECK-NEXT: stur w10, [x29, #-12]
; CHECK-NEXT: stp w9, w11, [sp, #12]