drm/i915/gt: Use parameterized RING_MI_MODE

We have both a parameterized RING_MI_MODE() macro and an RCS-specific
MI_MODE; drop the latter and use the former everywhere.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220209051140.1599643-4-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index cafb078..0bf8b45 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -70,6 +70,12 @@
 #define RING_NOPID(base)                       _MMIO((base) + 0x94)
 #define RING_HWSTAM(base)                      _MMIO((base) + 0x98)
 #define RING_MI_MODE(base)                     _MMIO((base) + 0x9c)
+#define   ASYNC_FLIP_PERF_DISABLE              REG_BIT(14)
+#define   MI_FLUSH_ENABLE                      REG_BIT(12)
+#define   TGL_NESTED_BB_EN                     REG_BIT(12)
+#define   MODE_IDLE                            REG_BIT(9)
+#define   STOP_RING                            REG_BIT(8)
+#define   VS_TIMER_DISPATCH                    REG_BIT(6)
 #define RING_IMR(base)                         _MMIO((base) + 0xa8)
 #define RING_EIR(base)                         _MMIO((base) + 0xb0)
 #define RING_EMR(base)                         _MMIO((base) + 0xb4)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 07a5a45..95c3f67 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -389,14 +389,6 @@
 #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)      ((x) << 1) /* gen8+ */
 #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH  (1 << 1) /* gen6 */
 
-#define MI_MODE                _MMIO(0x209c)
-# define VS_TIMER_DISPATCH                             (1 << 6)
-# define MI_FLUSH_ENABLE                               (1 << 12)
-# define TGL_NESTED_BB_EN                              (1 << 12)
-# define ASYNC_FLIP_PERF_DISABLE                       (1 << 14)
-# define MODE_IDLE                                     (1 << 9)
-# define STOP_RING                                     (1 << 8)
-
 #define GEN6_GT_MODE   _MMIO(0x20d0)
 #define GEN7_GT_MODE   _MMIO(0x7008)
 #define   GEN6_WIZ_HASHING(hi, lo)                     (((hi) << 9) | ((lo) << 7))

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 59ad231..eeda169 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -237,7 +237,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
        wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 
        /* WaDisableAsyncFlipPerfMode:bdw,chv */
-       wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+       wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
 
        /* WaDisablePartialInstShootdown:bdw,chv */
        wa_masked_en(wal, GEN8_ROW_CHICKEN,
@@ -2463,7 +2463,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
                 */
                wa_masked_en(wal,
-                            MI_MODE,
+                            RING_MI_MODE(RENDER_RING_BASE),
                             ASYNC_FLIP_PERF_DISABLE);
 
        if (GRAPHICS_VER(i915) == 6) {
@@ -2522,7 +2522,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
        if (IS_GRAPHICS_VER(i915, 4, 6))
                /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
-               wa_add(wal, MI_MODE,
+               wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
                       0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
                       /* XXX bit doesn't stick on Broadwater */
                       IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 850ebfa..dd8fdd5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1496,7 +1496,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
        /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
         * the chip from rc6 before touching it for real. MI_MODE is masked,
         * hence harmless to write 0 into. */
-       __raw_uncore_write32(uncore, MI_MODE, 0);
+       __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
 }
 
 static void