[AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.

llvm-svn: 265028

diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt
index 554418e..844d4a3 100644 (file)
--- a/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt
@@ -138,14 +138,14 @@
 # VI:   v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
 0x02 0x07 0x02 0x38
 
-# FIXME: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0xaa,0x01]
-#0x01 0x00 0x1c 0xd1 0x02 0x07 0xaa 0x01
+# VI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0xaa,0x01]
+0x01 0x00 0x1c 0xd1 0x02 0x07 0xaa 0x01
 
-# FIXME: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
-#0x01 0x00 0x1c 0xd1 0x02 0x07 0x0a 0x00
+# VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
+0x01 0x00 0x1c 0xd1 0x02 0x07 0x0a 0x00
 
-# FIXME: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
-#0x01 0x00 0x1c 0xd1 0x02 0x07 0x0a 0x00
+# VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
+0x01 0x00 0x1c 0xd1 0x02 0x07 0x0a 0x00
 
 # FIXME: v_addc_u32_e64 v1, s[0:1], v2, v3, -1 ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x06,0x03]
 #0x01 0x00 0x1c 0xd1 0x02 0x07 0x06 0x03
@@ -153,8 +153,8 @@
 # FIXME: v_addc_u32_e64 v1, vcc, v2, v3, -1 ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0x06,0x03]
 #0x01 0x6a 0x1c 0xd1 0x02 0x07 0x06 0x03
 
-# FIXME: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0xaa,0x01]
-#0x01 0x6a 0x1c 0xd1 0x02 0x07 0xaa 0x01
+# VI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0xaa,0x01]
+0x01 0x6a 0x1c 0xd1 0x02 0x07 0xaa 0x01
 
 # VI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3a]
 0x02 0x07 0x02 0x3a