bt-binding:pl080:remove arm pl080 compatible

remove arm pl080 compatible and add support
for starfive jh7110-pl080

Signed-off-by: William Qiu <william.qiu@starfivetech.com>

diff --git a/Documentation/devicetree/bindings/dma/starfive-pl080.yaml b/Documentation/devicetree/bindings/dma/starfive-pl080.yaml
new file mode 100644 (file)
index 0000000..5a804f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/starfive-pl080.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/starfive-sec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SEC controller Device Tree Bindings
+
+properties:
+    compatible:
+        const: starfive,jh7110-pl080
+
+    reg:
+        minItem: 1
+
+    reg-names:
+        maxItem: 1
+        const: sec_dma
+
+    interrupts:
+        minItem: 1
+
+    clocks:
+        minItem: 1
+        items:
+            -description:sec_hclk clock
+            -description:sec_ahb clock
+
+    clock-names:
+        minItem: 1
+        items:
+            -const:sec_hclk
+            -const:sec_ahb
+
+    resets:
+        minItem: 1
+        items:
+            -description:sec_hre reset
+
+    reset-names:
+        minItem: 1
+        items:
+            -const:sec_hre
+
+required:
+    - compatible
+    - reg
+    - reg-names
+    - interrupts
+    - clocks
+    - clock-names
+    - resets
+    - reset-names
+
+additionalProperties:false
+
+examples:
+    - |
+        sec_dma: sec_dma@16008000 {
+                       compatible = "starfive,pl080", "arm,pl080";
+                       reg = <0x0 0x16008000 0x0 0x4000>;
+                       reg-names = "sec_dma";
+                       interrupts = <29>;
+                       clocks = <&clkgen JH7110_SEC_HCLK>,
+                                <&clkgen JH7110_SEC_MISCAHB_CLK>;
+                       clock-names = "sec_hclk","sec_ahb";
+                       resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+                       reset-names = "sec_hre";
+                       lli-bus-interface-ahb1;
+                       mem-bus-interface-ahb1;
+                       memcpy-burst-size = <256>;
+                       memcpy-bus-width = <32>;
+                       #dma-cells = <2>;
+                       status = "disabled";
+               };

diff --git a/MAINTAINERS b/MAINTAINERS
index 3ef811f..639e0eb 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20856,3 +20856,8 @@ STARFIVE JH7110 SDIO
 M:     William Qiu <william.qiu@starfivetech.com>
 S:     Maintained
 F:     Documentation/devicetree/bindings/mmc/starfive,jh7110-sdio.yaml
+
+STARFIVE JH7110 SEC-DMA
+M:     William Qiu <william.qiu@starfivetech.com>
+S:     Maintained
+F:     Documentation/devicetree/bindings/dma/starfive-pl080.yaml

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index ed099ec..8872022 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -712,7 +712,7 @@
                };
 
                sec_dma: sec_dma@16008000 {
-                       compatible = "starfive,pl080", "arm,pl080", "arm,primecell";
+                       compatible = "starfive,jh7110-pl080", "arm,pl080";
                        reg = <0x0 0x16008000 0x0 0x4000>;
                        reg-names = "sec_dma";
                        interrupts = <29>;