5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_fastmul_tune =
5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
/* StrongARM has early execution of branches, so a sequence that is worth
3, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_xscale_tune =
3, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_9e_tune =
5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_v6t2_tune =
5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
/* Generic Cortex tuning. Use more specific tunings if appropriate. */
5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
1, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
false, /* Prefer constant pool. */
- arm_cortex_a5_branch_cost
+ arm_cortex_a5_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_cortex_a9_tune =
5, /* Max cond insns. */
ARM_PREFETCH_BENEFICIAL(4,32,32),
false, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};
const struct tune_params arm_fa726te_tune =
5, /* Max cond insns. */
ARM_PREFETCH_NOT_BENEFICIAL,
true, /* Prefer constant pool. */
- arm_default_branch_cost
+ arm_default_branch_cost,
+ false /* Prefer LDRD/STRD. */
};