clk: renesas: r8a779a0: Add RWDT clocks

And introduce critical clocks, too, because RWDT is one.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20201218173731.12839-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index d7825ad..f93ba9a 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -192,6 +192,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("vin37",        829,    R8A779A0_CLK_S1D1),
        DEF_MOD("vspd0",        830,    R8A779A0_CLK_S3D1),
        DEF_MOD("vspd1",        831,    R8A779A0_CLK_S3D1),
+       DEF_MOD("rwdt",         907,    R8A779A0_CLK_R),
        DEF_MOD("vspx0",        1028,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx1",        1029,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx2",        1030,   R8A779A0_CLK_S1D1),
@@ -269,6 +270,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
                                         __clk_get_name(parent), 0, mult, div);
 }
 
+static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
+       MOD_CLK_ID(907),        /* RWDT */
+};
+
 /*
  * CPG Clock Data
  */
@@ -319,6 +324,10 @@ const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
        .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
        .num_hw_mod_clks = 15 * 32,
 
+       /* Critical Module Clocks */
+       .crit_mod_clks          = r8a779a0_crit_mod_clks,
+       .num_crit_mod_clks      = ARRAY_SIZE(r8a779a0_crit_mod_clks),
+
        /* Callbacks */
        .init = r8a779a0_cpg_mssr_init,
        .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,