""
"
{
+ if (WORDS_BIG_ENDIAN)
+ return gen_mulsi3_big (operands[0], operands[1], operands[2]);
+ else
+ return gen_mulsi3_little (operands[0], operands[1], operands[2]);
+}")
+
+(define_expand "mulsi3_little"
+ [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
+ (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
+ (clobber (match_dup 3))
+ (set (subreg:SI (match_dup 3) 0)
+ (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
+ (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
+ "! WORDS_BIG_ENDIAN"
+ "
+{
+ operands[3] = gen_reg_rtx (DImode);
+ operands[4] = gen_reg_rtx (DImode);
+ operands[5] = gen_reg_rtx (DImode);
+}")
+
+(define_expand "mulsi3_big"
+ [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" ""))
+ (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" ""))
+ (clobber (match_dup 3))
+ (set (subreg:SI (match_dup 3) 0)
+ (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
+ (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
+ "WORDS_BIG_ENDIAN"
+ "
+{
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
operands[5] = gen_reg_rtx (DImode);