carl9170: Register maps, tx/rx descriptor formats and eeprom layout
authorChristian Lamparter <chunkeey@googlemail.com>
Sun, 5 Sep 2010 23:06:57 +0000 (01:06 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 14 Sep 2010 20:03:41 +0000 (16:03 -0400)
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/carl9170/eeprom.h [new file with mode: 0644]
drivers/net/wireless/ath/carl9170/fwcmd.h [new file with mode: 0644]
drivers/net/wireless/ath/carl9170/fwdesc.h [new file with mode: 0644]
drivers/net/wireless/ath/carl9170/hw.h [new file with mode: 0644]
drivers/net/wireless/ath/carl9170/phy.h [new file with mode: 0644]
drivers/net/wireless/ath/carl9170/wlan.h [new file with mode: 0644]

diff --git a/drivers/net/wireless/ath/carl9170/eeprom.h b/drivers/net/wireless/ath/carl9170/eeprom.h
new file mode 100644 (file)
index 0000000..7cff40a
--- /dev/null
@@ -0,0 +1,216 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * EEPROM layout
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __CARL9170_SHARED_EEPROM_H
+#define __CARL9170_SHARED_EEPROM_H
+
+#define AR9170_EEPROM_START            0x1600
+
+#define AR5416_MAX_CHAINS              2
+#define AR5416_MODAL_SPURS             5
+
+struct ar9170_eeprom_modal {
+       __le32  antCtrlChain[AR5416_MAX_CHAINS];
+       __le32  antCtrlCommon;
+       s8      antennaGainCh[AR5416_MAX_CHAINS];
+       u8      switchSettling;
+       u8      txRxAttenCh[AR5416_MAX_CHAINS];
+       u8      rxTxMarginCh[AR5416_MAX_CHAINS];
+       s8      adcDesiredSize;
+       s8      pgaDesiredSize;
+       u8      xlnaGainCh[AR5416_MAX_CHAINS];
+       u8      txEndToXpaOff;
+       u8      txEndToRxOn;
+       u8      txFrameToXpaOn;
+       u8      thresh62;
+       s8      noiseFloorThreshCh[AR5416_MAX_CHAINS];
+       u8      xpdGain;
+       u8      xpd;
+       s8      iqCalICh[AR5416_MAX_CHAINS];
+       s8      iqCalQCh[AR5416_MAX_CHAINS];
+       u8      pdGainOverlap;
+       u8      ob;
+       u8      db;
+       u8      xpaBiasLvl;
+       u8      pwrDecreaseFor2Chain;
+       u8      pwrDecreaseFor3Chain;
+       u8      txFrameToDataStart;
+       u8      txFrameToPaOn;
+       u8      ht40PowerIncForPdadc;
+       u8      bswAtten[AR5416_MAX_CHAINS];
+       u8      bswMargin[AR5416_MAX_CHAINS];
+       u8      swSettleHt40;
+       u8      reserved[22];
+       struct spur_channel {
+               __le16 spurChan;
+               u8      spurRangeLow;
+               u8      spurRangeHigh;
+       } __packed spur_channels[AR5416_MODAL_SPURS];
+} __packed;
+
+#define AR5416_NUM_PD_GAINS            4
+#define AR5416_PD_GAIN_ICEPTS          5
+
+struct ar9170_calibration_data_per_freq {
+       u8      pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+       u8      vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+} __packed;
+
+#define AR5416_NUM_5G_CAL_PIERS                8
+#define AR5416_NUM_2G_CAL_PIERS                4
+
+#define AR5416_NUM_5G_TARGET_PWRS      8
+#define AR5416_NUM_2G_CCK_TARGET_PWRS  3
+#define AR5416_NUM_2G_OFDM_TARGET_PWRS 4
+#define AR5416_MAX_NUM_TGT_PWRS                8
+
+struct ar9170_calibration_target_power_legacy {
+       u8      freq;
+       u8      power[4];
+} __packed;
+
+struct ar9170_calibration_target_power_ht {
+       u8      freq;
+       u8      power[8];
+} __packed;
+
+#define AR5416_NUM_CTLS                        24
+
+struct ar9170_calctl_edges {
+       u8      channel;
+#define AR9170_CALCTL_EDGE_FLAGS       0xC0
+       u8      power_flags;
+} __packed;
+
+#define AR5416_NUM_BAND_EDGES          8
+
+struct ar9170_calctl_data {
+       struct ar9170_calctl_edges
+               control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
+} __packed;
+
+struct ar9170_eeprom {
+       __le16  length;
+       __le16  checksum;
+       __le16  version;
+       u8      operating_flags;
+#define AR9170_OPFLAG_5GHZ             1
+#define AR9170_OPFLAG_2GHZ             2
+       u8      misc;
+       __le16  reg_domain[2];
+       u8      mac_address[6];
+       u8      rx_mask;
+       u8      tx_mask;
+       __le16  rf_silent;
+       __le16  bluetooth_options;
+       __le16  device_capabilities;
+       __le32  build_number;
+       u8      deviceType;
+       u8      reserved[33];
+
+       u8      customer_data[64];
+
+       struct ar9170_eeprom_modal
+               modal_header[2];
+
+       u8      cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
+       u8      cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
+
+       struct ar9170_calibration_data_per_freq
+               cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
+               cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
+
+       /* power calibration data */
+       struct ar9170_calibration_target_power_legacy
+               cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
+       struct ar9170_calibration_target_power_ht
+               cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
+               cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
+
+       struct ar9170_calibration_target_power_legacy
+               cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
+               cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
+       struct ar9170_calibration_target_power_ht
+               cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
+               cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
+
+       /* conformance testing limits */
+       u8      ctl_index[AR5416_NUM_CTLS];
+       struct ar9170_calctl_data
+               ctl_data[AR5416_NUM_CTLS];
+
+       u8      pad;
+       __le16  subsystem_id;
+} __packed;
+
+#define AR9170_LED_MODE_POWER_ON               0x0001
+#define AR9170_LED_MODE_RESERVED               0x0002
+#define AR9170_LED_MODE_DISABLE_STATE          0x0004
+#define AR9170_LED_MODE_OFF_IN_PSM             0x0008
+
+/* AR9170_LED_MODE BIT is set */
+#define AR9170_LED_MODE_FREQUENCY_S            4
+#define AR9170_LED_MODE_FREQUENCY              0x0030
+#define AR9170_LED_MODE_FREQUENCY_1HZ          0x0000
+#define AR9170_LED_MODE_FREQUENCY_0_5HZ                0x0010
+#define AR9170_LED_MODE_FREQUENCY_0_25HZ       0x0020
+#define AR9170_LED_MODE_FREQUENCY_0_125HZ      0x0030
+
+/* AR9170_LED_MODE BIT is not set */
+#define AR9170_LED_MODE_CONN_STATE_S           4
+#define AR9170_LED_MODE_CONN_STATE             0x0030
+#define AR9170_LED_MODE_CONN_STATE_FORCE_OFF   0x0000
+#define AR9170_LED_MODE_CONN_STATE_FORCE_ON    0x0010
+/* Idle off / Active on */
+#define AR9170_LED_MODE_CONN_STATE_IOFF_AON    0x0020
+/* Idle on / Active off */
+#define AR9170_LED_MODE_CONN_STATE_ION_AOFF    0x0010
+
+#define AR9170_LED_MODE_MODE                   0x0040
+#define AR9170_LED_MODE_RESERVED2              0x0080
+
+#define AR9170_LED_MODE_TON_SCAN_S             8
+#define AR9170_LED_MODE_TON_SCAN               0x0f00
+
+#define AR9170_LED_MODE_TOFF_SCAN_S            12
+#define AR9170_LED_MODE_TOFF_SCAN              0xf000
+
+struct ar9170_led_mode {
+       __le16 led;
+};
+
+#endif /* __CARL9170_SHARED_EEPROM_H */
diff --git a/drivers/net/wireless/ath/carl9170/fwcmd.h b/drivers/net/wireless/ath/carl9170/fwcmd.h
new file mode 100644 (file)
index 0000000..d4a4e1d
--- /dev/null
@@ -0,0 +1,268 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * Firmware command interface definitions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_FWCMD_H
+#define __CARL9170_SHARED_FWCMD_H
+
+#define        CARL9170_MAX_CMD_LEN            64
+#define        CARL9170_MAX_CMD_PAYLOAD_LEN    60
+
+#define CARL9170FW_API_MIN_VER         1
+#define CARL9170FW_API_MAX_VER         1
+
+enum carl9170_cmd_oids {
+       CARL9170_CMD_RREG               = 0x00,
+       CARL9170_CMD_WREG               = 0x01,
+       CARL9170_CMD_ECHO               = 0x02,
+       CARL9170_CMD_SWRST              = 0x03,
+       CARL9170_CMD_REBOOT             = 0x04,
+       CARL9170_CMD_BCN_CTRL           = 0x05,
+       CARL9170_CMD_READ_TSF           = 0x06,
+
+       /* CAM */
+       CARL9170_CMD_EKEY               = 0x10,
+       CARL9170_CMD_DKEY               = 0x11,
+
+       /* RF / PHY */
+       CARL9170_CMD_FREQUENCY          = 0x20,
+       CARL9170_CMD_RF_INIT            = 0x21,
+       CARL9170_CMD_SYNTH              = 0x22,
+       CARL9170_CMD_FREQ_START         = 0x23,
+       CARL9170_CMD_PSM                = 0x24,
+
+       /* Asychronous command flag */
+       CARL9170_CMD_ASYNC_FLAG         = 0x40,
+       CARL9170_CMD_WREG_ASYNC         = (CARL9170_CMD_WREG |
+                                          CARL9170_CMD_ASYNC_FLAG),
+       CARL9170_CMD_REBOOT_ASYNC       = (CARL9170_CMD_REBOOT |
+                                          CARL9170_CMD_ASYNC_FLAG),
+       CARL9170_CMD_BCN_CTRL_ASYNC     = (CARL9170_CMD_BCN_CTRL |
+                                          CARL9170_CMD_ASYNC_FLAG),
+       CARL9170_CMD_PSM_ASYNC          = (CARL9170_CMD_PSM |
+                                          CARL9170_CMD_ASYNC_FLAG),
+
+       /* responses and traps */
+       CARL9170_RSP_FLAG               = 0xc0,
+       CARL9170_RSP_PRETBTT            = 0xc0,
+       CARL9170_RSP_TXCOMP             = 0xc1,
+       CARL9170_RSP_BEACON_CONFIG      = 0xc2,
+       CARL9170_RSP_ATIM               = 0xc3,
+       CARL9170_RSP_WATCHDOG           = 0xc6,
+       CARL9170_RSP_TEXT               = 0xca,
+       CARL9170_RSP_HEXDUMP            = 0xcc,
+       CARL9170_RSP_RADAR              = 0xcd,
+       CARL9170_RSP_GPIO               = 0xce,
+       CARL9170_RSP_BOOT               = 0xcf,
+};
+
+struct carl9170_set_key_cmd {
+       __le16          user;
+       __le16          keyId;
+       __le16          type;
+       u8              macAddr[6];
+       u32             key[4];
+} __packed;
+#define CARL9170_SET_KEY_CMD_SIZE              28
+
+struct carl9170_disable_key_cmd {
+       __le16          user;
+       __le16          padding;
+} __packed;
+#define CARL9170_DISABLE_KEY_CMD_SIZE          4
+
+struct carl9170_u32_list {
+       u32     vals[0];
+} __packed;
+
+struct carl9170_reg_list {
+       __le32          regs[0];
+} __packed;
+
+struct carl9170_write_reg {
+       struct {
+               __le32          addr;
+               __le32          val;
+       } regs[0] __packed;
+} __packed;
+
+#define        CARL9170FW_PHY_HT_ENABLE                0x4
+#define        CARL9170FW_PHY_HT_DYN2040               0x8
+#define        CARL9170FW_PHY_HT_EXT_CHAN_OFF          0x3
+#define        CARL9170FW_PHY_HT_EXT_CHAN_OFF_S        2
+
+struct carl9170_rf_init {
+       __le32          freq;
+       u8              ht_settings;
+       u8              padding2[3];
+       __le32          delta_slope_coeff_exp;
+       __le32          delta_slope_coeff_man;
+       __le32          delta_slope_coeff_exp_shgi;
+       __le32          delta_slope_coeff_man_shgi;
+       __le32          finiteLoopCount;
+} __packed;
+#define CARL9170_RF_INIT_SIZE          28
+
+struct carl9170_rf_init_result {
+       __le32          ret;            /* AR9170_PHY_REG_AGC_CONTROL */
+} __packed;
+#define        CARL9170_RF_INIT_RESULT_SIZE    4
+
+#define        CARL9170_PSM_SLEEP              0x1000
+#define        CARL9170_PSM_SOFTWARE           0
+#define        CARL9170_PSM_WAKE               0 /* internally used. */
+#define        CARL9170_PSM_COUNTER            0xfff
+#define        CARL9170_PSM_COUNTER_S          0
+
+struct carl9170_psm {
+       __le32          state;
+} __packed;
+#define CARL9170_PSM_SIZE              4
+
+struct carl9170_bcn_ctrl_cmd {
+       __le32          vif_id;
+       __le32          mode;
+       __le32          bcn_addr;
+       __le32          bcn_len;
+} __packed;
+#define CARL9170_BCN_CTRL_CMD_SIZE     16
+
+#define CARL9170_BCN_CTRL_DRAIN        0
+#define CARL9170_BCN_CTRL_CAB_TRIGGER  1
+
+struct carl9170_cmd_head {
+       union {
+               struct {
+                       u8      len;
+                       u8      cmd;
+                       u8      seq;
+                       u8      ext;
+               } __packed;
+
+               u32 hdr_data;
+       } __packed;
+} __packed;
+
+struct carl9170_cmd {
+       struct carl9170_cmd_head hdr;
+       union {
+               struct carl9170_set_key_cmd     setkey;
+               struct carl9170_disable_key_cmd disablekey;
+               struct carl9170_u32_list        echo;
+               struct carl9170_reg_list        rreg;
+               struct carl9170_write_reg       wreg;
+               struct carl9170_rf_init         rf_init;
+               struct carl9170_psm             psm;
+               struct carl9170_bcn_ctrl_cmd    bcn_ctrl;
+               u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
+       } __packed;
+} __packed;
+
+#define        CARL9170_TX_STATUS_QUEUE        3
+#define        CARL9170_TX_STATUS_QUEUE_S      0
+#define        CARL9170_TX_STATUS_RIX_S        2
+#define        CARL9170_TX_STATUS_RIX          (3 << CARL9170_TX_STATUS_RIX_S)
+#define        CARL9170_TX_STATUS_TRIES_S      4
+#define        CARL9170_TX_STATUS_TRIES        (7 << CARL9170_TX_STATUS_TRIES_S)
+#define        CARL9170_TX_STATUS_SUCCESS      0x80
+
+/*
+ * NOTE:
+ * Both structs [carl9170_tx_status and _carl9170_tx_status]
+ * need to be "bit for bit" in sync.
+ */
+struct carl9170_tx_status {
+       /*
+        * Beware of compiler bugs in all gcc pre 4.4!
+        */
+
+       u8 cookie;
+       u8 queue:2;
+       u8 rix:2;
+       u8 tries:3;
+       u8 success:1;
+} __packed;
+struct _carl9170_tx_status {
+       /*
+        * This version should be immune to all alignment bugs.
+        */
+
+       u8 cookie;
+       u8 info;
+} __packed;
+#define CARL9170_TX_STATUS_SIZE                2
+
+#define        CARL9170_RSP_TX_STATUS_NUM      (CARL9170_MAX_CMD_PAYLOAD_LEN / \
+                                        sizeof(struct _carl9170_tx_status))
+
+#define        CARL9170_TX_MAX_RATE_TRIES      7
+
+#define        CARL9170_TX_MAX_RATES           4
+#define        CARL9170_TX_MAX_RETRY_RATES     (CARL9170_TX_MAX_RATES - 1)
+#define        CARL9170_ERR_MAGIC              "ERR:"
+#define        CARL9170_BUG_MAGIC              "BUG:"
+
+struct carl9170_gpio {
+       __le32 gpio;
+} __packed;
+#define CARL9170_GPIO_SIZE             4
+
+struct carl9170_tsf_rsp {
+       union {
+               __le32 tsf[2];
+               __le64 tsf_64;
+       } __packed;
+} __packed;
+#define CARL9170_TSF_RSP_SIZE          8
+
+struct carl9170_rsp {
+       struct carl9170_cmd_head hdr;
+
+       union {
+               struct carl9170_rf_init_result  rf_init_res;
+               struct carl9170_u32_list        rreg_res;
+               struct carl9170_u32_list        echo;
+               struct carl9170_tx_status       tx_status[0];
+               struct _carl9170_tx_status      _tx_status[0];
+               struct carl9170_gpio            gpio;
+               struct carl9170_tsf_rsp         tsf;
+               struct carl9170_psm             psm;
+               u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
+       } __packed;
+} __packed;
+
+#endif /* __CARL9170_SHARED_FWCMD_H */
diff --git a/drivers/net/wireless/ath/carl9170/fwdesc.h b/drivers/net/wireless/ath/carl9170/fwdesc.h
new file mode 100644 (file)
index 0000000..7cd8117
--- /dev/null
@@ -0,0 +1,237 @@
+/*
+ * Shared CARL9170 Header
+ *
+ * Firmware descriptor format
+ *
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ */
+
+#ifndef __CARL9170_SHARED_FWDESC_H
+#define __CARL9170_SHARED_FWDESC_H
+
+/* NOTE: Don't mess with the order of the flags! */
+enum carl9170fw_feature_list {
+       /* Always set */
+       CARL9170FW_DUMMY_FEATURE,
+
+       /*
+        * Indicates that this image has special boot block which prevents
+        * legacy drivers to drive the firmware.
+        */
+       CARL9170FW_MINIBOOT,
+
+       /* usb registers are initialized by the firmware */
+       CARL9170FW_USB_INIT_FIRMWARE,
+
+       /* command traps & notifications are send through EP2 */
+       CARL9170FW_USB_RESP_EP2,
+
+       /* usb download (app -> fw) stream */
+       CARL9170FW_USB_DOWN_STREAM,
+
+       /* usb upload (fw -> app) stream */
+       CARL9170FW_USB_UP_STREAM,
+
+       /* unusable - reserved to flag non-functional debug firmwares */
+       CARL9170FW_UNUSABLE,
+
+       /* AR9170_CMD_RF_INIT, AR9170_CMD_FREQ_START, AR9170_CMD_FREQUENCY */
+       CARL9170FW_COMMAND_PHY,
+
+       /* AR9170_CMD_EKEY, AR9170_CMD_DKEY */
+       CARL9170FW_COMMAND_CAM,
+
+       /* Firmware has a software Content After Beacon Queueing mechanism */
+       CARL9170FW_WLANTX_CAB,
+
+       /* The firmware is capable of responding to incoming BAR frames */
+       CARL9170FW_HANDLE_BACK_REQ,
+
+       /* GPIO Interrupt | CARL9170_RSP_GPIO */
+       CARL9170FW_GPIO_INTERRUPT,
+
+       /* Firmware PSM support | CARL9170_CMD_PSM */
+       CARL9170FW_PSM,
+
+       /* KEEP LAST */
+       __CARL9170FW_FEATURE_NUM
+};
+
+#define OTUS_MAGIC     "OTAR"
+#define MOTD_MAGIC     "MOTD"
+#define FIX_MAGIC      "FIX\0"
+#define DBG_MAGIC      "DBG\0"
+#define CHK_MAGIC      "CHK\0"
+#define LAST_MAGIC     "LAST"
+
+#define CARL9170FW_SET_DAY(d) (((d) - 1) % 31)
+#define CARL9170FW_SET_MONTH(m) ((((m) - 1) % 12) * 31)
+#define CARL9170FW_SET_YEAR(y) (((y) - 10) * 372)
+
+#define CARL9170FW_GET_DAY(d) (((d) % 31) + 1)
+#define CARL9170FW_GET_MONTH(m) ((((m) / 31) % 12) + 1)
+#define CARL9170FW_GET_YEAR(y) ((y) / 372 + 10)
+
+struct carl9170fw_desc_head {
+       u8      magic[4];
+       __le16 length;
+       u8 min_ver;
+       u8 cur_ver;
+} __packed;
+#define CARL9170FW_DESC_HEAD_SIZE                      \
+       (sizeof(struct carl9170fw_desc_head))
+
+#define CARL9170FW_OTUS_DESC_MIN_VER           6
+#define CARL9170FW_OTUS_DESC_CUR_VER           6
+struct carl9170fw_otus_desc {
+       struct carl9170fw_desc_head head;
+       __le32 feature_set;
+       __le32 fw_address;
+       __le32 bcn_addr;
+       __le16 bcn_len;
+       __le16 miniboot_size;
+       __le16 tx_frag_len;
+       __le16 rx_max_frame_len;
+       u8 tx_descs;
+       u8 cmd_bufs;
+       u8 api_ver;
+       u8 vif_num;
+} __packed;
+#define CARL9170FW_OTUS_DESC_SIZE                      \
+       (sizeof(struct carl9170fw_otus_desc))
+
+#define CARL9170FW_MOTD_STRING_LEN                     24
+#define CARL9170FW_MOTD_RELEASE_LEN                    20
+#define CARL9170FW_MOTD_DESC_MIN_VER                   1
+#define CARL9170FW_MOTD_DESC_CUR_VER                   2
+struct carl9170fw_motd_desc {
+       struct carl9170fw_desc_head head;
+       __le32 fw_year_month_day;
+       char desc[CARL9170FW_MOTD_STRING_LEN];
+       char release[CARL9170FW_MOTD_RELEASE_LEN];
+} __packed;
+#define CARL9170FW_MOTD_DESC_SIZE                      \
+       (sizeof(struct carl9170fw_motd_desc))
+
+#define CARL9170FW_FIX_DESC_MIN_VER                    1
+#define CARL9170FW_FIX_DESC_CUR_VER                    2
+struct carl9170fw_fix_entry {
+       __le32 address;
+       __le32 mask;
+       __le32 value;
+} __packed;
+
+struct carl9170fw_fix_desc {
+       struct carl9170fw_desc_head head;
+       struct carl9170fw_fix_entry data[0];
+} __packed;
+#define CARL9170FW_FIX_DESC_SIZE                       \
+       (sizeof(struct carl9170fw_fix_desc))
+
+#define CARL9170FW_DBG_DESC_MIN_VER                    1
+#define CARL9170FW_DBG_DESC_CUR_VER                    2
+struct carl9170fw_dbg_desc {
+       struct carl9170fw_desc_head head;
+
+       __le32 bogoclock_addr;
+       __le32 counter_addr;
+       __le32 rx_total_addr;
+       __le32 rx_overrun_addr;
+
+       /* Put your debugging definitions here */
+} __packed;
+#define CARL9170FW_DBG_DESC_SIZE                       \
+       (sizeof(struct carl9170fw_dbg_desc))
+
+#define CARL9170FW_CHK_DESC_MIN_VER                    1
+#define CARL9170FW_CHK_DESC_CUR_VER                    2
+struct carl9170fw_chk_desc {
+       struct carl9170fw_desc_head head;
+       __le32 fw_crc32;
+       __le32 hdr_crc32;
+} __packed;
+#define CARL9170FW_CHK_DESC_SIZE                       \
+       (sizeof(struct carl9170fw_chk_desc))
+
+#define CARL9170FW_LAST_DESC_MIN_VER                   1
+#define CARL9170FW_LAST_DESC_CUR_VER                   2
+struct carl9170fw_last_desc {
+       struct carl9170fw_desc_head head;
+} __packed;
+#define CARL9170FW_LAST_DESC_SIZE                      \
+       (sizeof(struct carl9170fw_fix_desc))
+
+#define CARL9170FW_DESC_MAX_LENGTH                     8192
+
+#define CARL9170FW_FILL_DESC(_magic, _length, _min_ver, _cur_ver)      \
+       .head = {                                                       \
+               .magic = _magic,                                        \
+               .length = cpu_to_le16(_length),                         \
+               .min_ver = _min_ver,                                    \
+               .cur_ver = _cur_ver,                                    \
+       }
+
+static inline void carl9170fw_fill_desc(struct carl9170fw_desc_head *head,
+                                        u8 magic[4], __le16 length,
+                                        u8 min_ver, u8 cur_ver)
+{
+       head->magic[0] = magic[0];
+       head->magic[1] = magic[1];
+       head->magic[2] = magic[2];
+       head->magic[3] = magic[3];
+
+       head->length = length;
+       head->min_ver = min_ver;
+       head->cur_ver = cur_ver;
+}
+
+#define carl9170fw_for_each_hdr(desc, fw_desc)                         \
+       for (desc = fw_desc;                                            \
+            memcmp(desc->magic, LAST_MAGIC, 4) &&                      \
+            le16_to_cpu(desc->length) >= CARL9170FW_DESC_HEAD_SIZE &&  \
+            le16_to_cpu(desc->length) < CARL9170FW_DESC_MAX_LENGTH;    \
+            desc = (void *)((unsigned long)desc + le16_to_cpu(desc->length)))
+
+#define CHECK_HDR_VERSION(head, _min_ver)                              \
+       (((head)->cur_ver < _min_ver) || ((head)->min_ver > _min_ver))  \
+
+static inline bool carl9170fw_supports(__le32 list, u8 feature)
+{
+       return le32_to_cpu(list) & BIT(feature);
+}
+
+static inline bool carl9170fw_desc_cmp(const struct carl9170fw_desc_head *head,
+                                      const u8 descid[4], u16 min_len,
+                                      u8 compatible_revision)
+{
+       if (descid[0] == head->magic[0] && descid[1] == head->magic[1] &&
+           descid[2] == head->magic[2] && descid[3] == head->magic[3] &&
+           !CHECK_HDR_VERSION(head, compatible_revision) &&
+           (le16_to_cpu(head->length) >= min_len))
+               return true;
+
+       return false;
+}
+
+#define CARL9170FW_MIN_SIZE    32
+#define CARL9170FW_MAX_SIZE    16384
+
+static inline bool carl9170fw_size_check(unsigned int len)
+{
+       return (len <= CARL9170FW_MAX_SIZE && len >= CARL9170FW_MIN_SIZE);
+}
+
+#endif /* __CARL9170_SHARED_FWDESC_H */
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h
new file mode 100644 (file)
index 0000000..b1292ac
--- /dev/null
@@ -0,0 +1,736 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * Register map, hardware-specific definitions
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_HW_H
+#define __CARL9170_SHARED_HW_H
+
+/* High Speed UART */
+#define        AR9170_UART_REG_BASE                    0x1c0000
+
+/* Definitions of interrupt registers */
+#define        AR9170_UART_REG_RX_BUFFER               (AR9170_UART_REG_BASE + 0x000)
+#define        AR9170_UART_REG_TX_HOLDING              (AR9170_UART_REG_BASE + 0x004)
+#define        AR9170_UART_REG_FIFO_CONTROL            (AR9170_UART_REG_BASE + 0x010)
+#define                AR9170_UART_FIFO_CTRL_RESET_RX_FIFO     0x02
+#define                AR9170_UART_FIFO_CTRL_RESET_TX_FIFO     0x04
+
+#define        AR9170_UART_REG_LINE_CONTROL            (AR9170_UART_REG_BASE + 0x014)
+#define        AR9170_UART_REG_MODEM_CONTROL           (AR9170_UART_REG_BASE + 0x018)
+#define                AR9170_UART_MODEM_CTRL_DTR_BIT          0x01
+#define                AR9170_UART_MODEM_CTRL_RTS_BIT          0x02
+#define                AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK       0x10
+#define                AR9170_UART_MODEM_CTRL_AUTO_RTS         0x20
+#define                AR9170_UART_MODEM_CTRL_AUTO_CTR         0x40
+
+#define        AR9170_UART_REG_LINE_STATUS             (AR9170_UART_REG_BASE + 0x01c)
+#define                AR9170_UART_LINE_STS_RX_DATA_READY      0x01
+#define                AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN  0x02
+#define                AR9170_UART_LINE_STS_RX_BREAK_IND       0x10
+#define                AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY 0x20
+#define                AR9170_UART_LINE_STS_TRANSMITTER_EMPTY  0x40
+
+#define        AR9170_UART_REG_MODEM_STATUS            (AR9170_UART_REG_BASE + 0x020)
+#define                AR9170_UART_MODEM_STS_CTS_CHANGE        0x01
+#define                AR9170_UART_MODEM_STS_DSR_CHANGE        0x02
+#define                AR9170_UART_MODEM_STS_DCD_CHANGE        0x08
+#define                AR9170_UART_MODEM_STS_CTS_COMPL         0x10
+#define                AR9170_UART_MODEM_STS_DSR_COMPL         0x20
+#define                AR9170_UART_MODEM_STS_DCD_COMPL         0x80
+
+#define        AR9170_UART_REG_SCRATCH                 (AR9170_UART_REG_BASE + 0x024)
+#define        AR9170_UART_REG_DIVISOR_LSB             (AR9170_UART_REG_BASE + 0x028)
+#define        AR9170_UART_REG_DIVISOR_MSB             (AR9170_UART_REG_BASE + 0x02c)
+#define        AR9170_UART_REG_WORD_RX_BUFFER          (AR9170_UART_REG_BASE + 0x034)
+#define        AR9170_UART_REG_WORD_TX_HOLDING         (AR9170_UART_REG_BASE + 0x038)
+#define        AR9170_UART_REG_FIFO_COUNT              (AR9170_UART_REG_BASE + 0x03c)
+#define        AR9170_UART_REG_REMAINDER               (AR9170_UART_REG_BASE + 0x04c)
+
+/* Timer */
+#define        AR9170_TIMER_REG_BASE                   0x1c1000
+
+#define        AR9170_TIMER_REG_WATCH_DOG              (AR9170_TIMER_REG_BASE + 0x000)
+#define        AR9170_TIMER_REG_TIMER0                 (AR9170_TIMER_REG_BASE + 0x010)
+#define        AR9170_TIMER_REG_TIMER1                 (AR9170_TIMER_REG_BASE + 0x014)
+#define        AR9170_TIMER_REG_TIMER2                 (AR9170_TIMER_REG_BASE + 0x018)
+#define        AR9170_TIMER_REG_TIMER3                 (AR9170_TIMER_REG_BASE + 0x01c)
+#define        AR9170_TIMER_REG_TIMER4                 (AR9170_TIMER_REG_BASE + 0x020)
+#define        AR9170_TIMER_REG_CONTROL                (AR9170_TIMER_REG_BASE + 0x024)
+#define                AR9170_TIMER_CTRL_DISABLE_CLOCK         0x100
+
+#define        AR9170_TIMER_REG_INTERRUPT              (AR9170_TIMER_REG_BASE + 0x028)
+#define                AR9170_TIMER_INT_TIMER0                 0x001
+#define                AR9170_TIMER_INT_TIMER1                 0x002
+#define                AR9170_TIMER_INT_TIMER2                 0x004
+#define                AR9170_TIMER_INT_TIMER3                 0x008
+#define                AR9170_TIMER_INT_TIMER4                 0x010
+#define                AR9170_TIMER_INT_TICK_TIMER             0x100
+
+#define        AR9170_TIMER_REG_TICK_TIMER             (AR9170_TIMER_REG_BASE + 0x030)
+#define        AR9170_TIMER_REG_CLOCK_LOW              (AR9170_TIMER_REG_BASE + 0x040)
+#define        AR9170_TIMER_REG_CLOCK_HIGH             (AR9170_TIMER_REG_BASE + 0x044)
+
+#define        AR9170_MAC_REG_BASE                     0x1c3000
+
+#define        AR9170_MAC_REG_POWER_STATE_CTRL         (AR9170_MAC_REG_BASE + 0x500)
+#define                AR9170_MAC_POWER_STATE_CTRL_RESET       0x20
+
+#define        AR9170_MAC_REG_MAC_POWER_STATE_CTRL     (AR9170_MAC_REG_BASE + 0x50c)
+
+#define        AR9170_MAC_REG_INT_CTRL                 (AR9170_MAC_REG_BASE + 0x510)
+#define                AR9170_MAC_INT_TXC                      BIT(0)
+#define                AR9170_MAC_INT_RXC                      BIT(1)
+#define                AR9170_MAC_INT_RETRY_FAIL               BIT(2)
+#define                AR9170_MAC_INT_WAKEUP                   BIT(3)
+#define                AR9170_MAC_INT_ATIM                     BIT(4)
+#define                AR9170_MAC_INT_DTIM                     BIT(5)
+#define                AR9170_MAC_INT_CFG_BCN                  BIT(6)
+#define                AR9170_MAC_INT_ABORT                    BIT(7)
+#define                AR9170_MAC_INT_QOS                      BIT(8)
+#define                AR9170_MAC_INT_MIMO_PS                  BIT(9)
+#define                AR9170_MAC_INT_KEY_GEN                  BIT(10)
+#define                AR9170_MAC_INT_DECRY_NOUSER             BIT(11)
+#define                AR9170_MAC_INT_RADAR                    BIT(12)
+#define                AR9170_MAC_INT_QUIET_FRAME              BIT(13)
+#define                AR9170_MAC_INT_PRETBTT                  BIT(14)
+
+#define        AR9170_MAC_REG_TSF_L                    (AR9170_MAC_REG_BASE + 0x514)
+#define        AR9170_MAC_REG_TSF_H                    (AR9170_MAC_REG_BASE + 0x518)
+
+#define        AR9170_MAC_REG_ATIM_WINDOW              (AR9170_MAC_REG_BASE + 0x51c)
+#define                AR9170_MAC_ATIM_PERIOD_S                0
+#define                AR9170_MAC_ATIM_PERIOD                  0x0000ffff
+
+#define        AR9170_MAC_REG_BCN_PERIOD               (AR9170_MAC_REG_BASE + 0x520)
+#define                AR9170_MAC_BCN_PERIOD_S                 0
+#define                AR9170_MAC_BCN_PERIOD                   0x0000ffff
+#define                AR9170_MAC_BCN_DTIM_S                   16
+#define                AR9170_MAC_BCN_DTIM                     0x00ff0000
+#define                AR9170_MAC_BCN_AP_MODE                  BIT(24)
+#define                AR9170_MAC_BCN_IBSS_MODE                BIT(25)
+#define                AR9170_MAC_BCN_PWR_MGT                  BIT(26)
+#define                AR9170_MAC_BCN_STA_PS                   BIT(27)
+
+#define        AR9170_MAC_REG_PRETBTT                  (AR9170_MAC_REG_BASE + 0x524)
+#define                AR9170_MAC_PRETBTT_S                    0
+#define                AR9170_MAC_PRETBTT                      0x0000ffff
+#define                AR9170_MAC_PRETBTT2_S                   16
+#define                AR9170_MAC_PRETBTT2                     0xffff0000
+
+#define        AR9170_MAC_REG_MAC_ADDR_L               (AR9170_MAC_REG_BASE + 0x610)
+#define        AR9170_MAC_REG_MAC_ADDR_H               (AR9170_MAC_REG_BASE + 0x614)
+#define        AR9170_MAC_REG_BSSID_L                  (AR9170_MAC_REG_BASE + 0x618)
+#define        AR9170_MAC_REG_BSSID_H                  (AR9170_MAC_REG_BASE + 0x61c)
+
+#define        AR9170_MAC_REG_GROUP_HASH_TBL_L         (AR9170_MAC_REG_BASE + 0x624)
+#define        AR9170_MAC_REG_GROUP_HASH_TBL_H         (AR9170_MAC_REG_BASE + 0x628)
+
+#define        AR9170_MAC_REG_RX_TIMEOUT               (AR9170_MAC_REG_BASE + 0x62c)
+
+#define        AR9170_MAC_REG_BASIC_RATE               (AR9170_MAC_REG_BASE + 0x630)
+#define        AR9170_MAC_REG_MANDATORY_RATE           (AR9170_MAC_REG_BASE + 0x634)
+#define        AR9170_MAC_REG_RTS_CTS_RATE             (AR9170_MAC_REG_BASE + 0x638)
+#define        AR9170_MAC_REG_BACKOFF_PROTECT          (AR9170_MAC_REG_BASE + 0x63c)
+#define        AR9170_MAC_REG_RX_THRESHOLD             (AR9170_MAC_REG_BASE + 0x640)
+#define        AR9170_MAC_REG_AFTER_PNP                (AR9170_MAC_REG_BASE + 0x648)
+#define        AR9170_MAC_REG_RX_PE_DELAY              (AR9170_MAC_REG_BASE + 0x64c)
+
+#define        AR9170_MAC_REG_DYNAMIC_SIFS_ACK         (AR9170_MAC_REG_BASE + 0x658)
+#define        AR9170_MAC_REG_SNIFFER                  (AR9170_MAC_REG_BASE + 0x674)
+#define                AR9170_MAC_SNIFFER_ENABLE_PROMISC       BIT(0)
+#define                AR9170_MAC_SNIFFER_DEFAULTS             0x02000000
+#define        AR9170_MAC_REG_ENCRYPTION               (AR9170_MAC_REG_BASE + 0x678)
+#define                AR9170_MAC_ENCRYPTION_RX_SOFTWARE       BIT(3)
+#define                AR9170_MAC_ENCRYPTION_DEFAULTS          0x70
+
+#define        AR9170_MAC_REG_MISC_680                 (AR9170_MAC_REG_BASE + 0x680)
+#define        AR9170_MAC_REG_MISC_684                 (AR9170_MAC_REG_BASE + 0x684)
+#define        AR9170_MAC_REG_TX_UNDERRUN              (AR9170_MAC_REG_BASE + 0x688)
+
+#define        AR9170_MAC_REG_FRAMETYPE_FILTER         (AR9170_MAC_REG_BASE + 0x68c)
+#define                AR9170_MAC_FTF_ASSOC_REQ                BIT(0)
+#define                AR9170_MAC_FTF_ASSOC_RESP               BIT(1)
+#define                AR9170_MAC_FTF_REASSOC_REQ              BIT(2)
+#define                AR9170_MAC_FTF_REASSOC_RESP             BIT(3)
+#define                AR9170_MAC_FTF_PRB_REQ                  BIT(4)
+#define                AR9170_MAC_FTF_PRB_RESP                 BIT(5)
+#define                AR9170_MAC_FTF_BIT6                     BIT(6)
+#define                AR9170_MAC_FTF_BIT7                     BIT(7)
+#define                AR9170_MAC_FTF_BEACON                   BIT(8)
+#define                AR9170_MAC_FTF_ATIM                     BIT(9)
+#define                AR9170_MAC_FTF_DEASSOC                  BIT(10)
+#define                AR9170_MAC_FTF_AUTH                     BIT(11)
+#define                AR9170_MAC_FTF_DEAUTH                   BIT(12)
+#define                AR9170_MAC_FTF_BIT13                    BIT(13)
+#define                AR9170_MAC_FTF_BIT14                    BIT(14)
+#define                AR9170_MAC_FTF_BIT15                    BIT(15)
+#define                AR9170_MAC_FTF_BAR                      BIT(24)
+#define                AR9170_MAC_FTF_BA                       BIT(25)
+#define                AR9170_MAC_FTF_PSPOLL                   BIT(26)
+#define                AR9170_MAC_FTF_RTS                      BIT(27)
+#define                AR9170_MAC_FTF_CTS                      BIT(28)
+#define                AR9170_MAC_FTF_ACK                      BIT(29)
+#define                AR9170_MAC_FTF_CFE                      BIT(30)
+#define                AR9170_MAC_FTF_CFE_ACK                  BIT(31)
+#define                AR9170_MAC_FTF_DEFAULTS                 0x0500ffff
+#define                AR9170_MAC_FTF_MONITOR                  0xff00ffff
+
+#define        AR9170_MAC_REG_ACK_EXTENSION            (AR9170_MAC_REG_BASE + 0x690)
+#define        AR9170_MAC_REG_ACK_TPC                  (AR9170_MAC_REG_BASE + 0x694)
+#define        AR9170_MAC_REG_EIFS_AND_SIFS            (AR9170_MAC_REG_BASE + 0x698)
+#define        AR9170_MAC_REG_RX_TIMEOUT_COUNT         (AR9170_MAC_REG_BASE + 0x69c)
+#define        AR9170_MAC_REG_RX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6a0)
+#define        AR9170_MAC_REG_RX_CRC32                 (AR9170_MAC_REG_BASE + 0x6a4)
+#define        AR9170_MAC_REG_RX_CRC16                 (AR9170_MAC_REG_BASE + 0x6a8)
+#define        AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI    (AR9170_MAC_REG_BASE + 0x6ac)
+#define        AR9170_MAC_REG_RX_OVERRUN               (AR9170_MAC_REG_BASE + 0x6b0)
+#define        AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL    (AR9170_MAC_REG_BASE + 0x6bc)
+#define AR9170_MAC_REG_TX_BLOCKACKS            (AR9170_MAC_REG_BASE + 0x6c0)
+#define AR9170_MAC_REG_NAV_COUNT               (AR9170_MAC_REG_BASE + 0x6c4)
+#define AR9170_MAC_REG_BACKOFF_STATUS          (AR9170_MAC_REG_BASE + 0x6c8)
+#define        AR9170_MAC_REG_TX_RETRY                 (AR9170_MAC_REG_BASE + 0x6cc)
+
+#define AR9170_MAC_REG_TX_COMPLETE             (AR9170_MAC_REG_BASE + 0x6d4)
+
+#define        AR9170_MAC_REG_CHANNEL_BUSY             (AR9170_MAC_REG_BASE + 0x6e8)
+#define        AR9170_MAC_REG_EXT_BUSY                 (AR9170_MAC_REG_BASE + 0x6ec)
+
+#define        AR9170_MAC_REG_SLOT_TIME                (AR9170_MAC_REG_BASE + 0x6f0)
+#define        AR9170_MAC_REG_TX_TOTAL                 (AR9170_MAC_REG_BASE + 0x6f4)
+#define AR9170_MAC_REG_ACK_FC                  (AR9170_MAC_REG_BASE + 0x6f8)
+
+#define        AR9170_MAC_REG_CAM_MODE                 (AR9170_MAC_REG_BASE + 0x700)
+#define                AR9170_MAC_CAM_IBSS                     0xe0
+#define                AR9170_MAC_CAM_AP                       0xa1
+#define                AR9170_MAC_CAM_STA                      0x2
+#define                AR9170_MAC_CAM_AP_WDS                   0x3
+#define                AR9170_MAC_CAM_DEFAULTS                 (0xf << 24)
+#define                AR9170_MAC_CAM_HOST_PENDING             0x80000000
+
+#define        AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L      (AR9170_MAC_REG_BASE + 0x704)
+#define        AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H      (AR9170_MAC_REG_BASE + 0x708)
+
+#define        AR9170_MAC_REG_CAM_ADDR                 (AR9170_MAC_REG_BASE + 0x70c)
+#define                AR9170_MAC_CAM_ADDR_WRITE               0x80000000
+#define        AR9170_MAC_REG_CAM_DATA0                (AR9170_MAC_REG_BASE + 0x720)
+#define        AR9170_MAC_REG_CAM_DATA1                (AR9170_MAC_REG_BASE + 0x724)
+#define        AR9170_MAC_REG_CAM_DATA2                (AR9170_MAC_REG_BASE + 0x728)
+#define        AR9170_MAC_REG_CAM_DATA3                (AR9170_MAC_REG_BASE + 0x72c)
+
+#define        AR9170_MAC_REG_CAM_DBG0                 (AR9170_MAC_REG_BASE + 0x730)
+#define        AR9170_MAC_REG_CAM_DBG1                 (AR9170_MAC_REG_BASE + 0x734)
+#define        AR9170_MAC_REG_CAM_DBG2                 (AR9170_MAC_REG_BASE + 0x738)
+#define        AR9170_MAC_REG_CAM_STATE                (AR9170_MAC_REG_BASE + 0x73c)
+#define                AR9170_MAC_CAM_STATE_READ_PENDING       0x40000000
+#define                AR9170_MAC_CAM_STATE_WRITE_PENDING      0x80000000
+
+#define        AR9170_MAC_REG_CAM_TXKEY                (AR9170_MAC_REG_BASE + 0x740)
+#define        AR9170_MAC_REG_CAM_RXKEY                (AR9170_MAC_REG_BASE + 0x750)
+
+#define        AR9170_MAC_REG_CAM_TX_ENC_TYPE          (AR9170_MAC_REG_BASE + 0x760)
+#define        AR9170_MAC_REG_CAM_RX_ENC_TYPE          (AR9170_MAC_REG_BASE + 0x770)
+#define        AR9170_MAC_REG_CAM_TX_SERACH_HIT        (AR9170_MAC_REG_BASE + 0x780)
+#define        AR9170_MAC_REG_CAM_RX_SERACH_HIT        (AR9170_MAC_REG_BASE + 0x790)
+
+#define        AR9170_MAC_REG_AC0_CW                   (AR9170_MAC_REG_BASE + 0xb00)
+#define        AR9170_MAC_REG_AC1_CW                   (AR9170_MAC_REG_BASE + 0xb04)
+#define        AR9170_MAC_REG_AC2_CW                   (AR9170_MAC_REG_BASE + 0xb08)
+#define        AR9170_MAC_REG_AC3_CW                   (AR9170_MAC_REG_BASE + 0xb0c)
+#define        AR9170_MAC_REG_AC4_CW                   (AR9170_MAC_REG_BASE + 0xb10)
+#define        AR9170_MAC_REG_AC2_AC1_AC0_AIFS         (AR9170_MAC_REG_BASE + 0xb14)
+#define        AR9170_MAC_REG_AC4_AC3_AC2_AIFS         (AR9170_MAC_REG_BASE + 0xb18)
+#define AR9170_MAC_REG_TXOP_ACK_EXTENSION      (AR9170_MAC_REG_BASE + 0xb1c)
+#define AR9170_MAC_REG_TXOP_ACK_INTERVAL       (AR9170_MAC_REG_BASE + 0xb20)
+#define AR9170_MAC_REG_CONTENTION_POINT                (AR9170_MAC_REG_BASE + 0xb24)
+#define        AR9170_MAC_REG_RETRY_MAX                (AR9170_MAC_REG_BASE + 0xb28)
+#define AR9170_MAC_REG_TID_CFACK_CFEND_RATE    (AR9170_MAC_REG_BASE + 0xb2c)
+#define        AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND      (AR9170_MAC_REG_BASE + 0xb30)
+#define AR9170_MAC_REG_TKIP_TSC                        (AR9170_MAC_REG_BASE + 0xb34)
+#define AR9170_MAC_REG_TXOP_DURATION           (AR9170_MAC_REG_BASE + 0xb38)
+#define AR9170_MAC_REG_TX_QOS_THRESHOLD                (AR9170_MAC_REG_BASE + 0xb3c)
+#define        AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA (AR9170_MAC_REG_BASE + 0xb40)
+#define                AR9170_MAC_VIRTUAL_CCA_Q0               BIT(15)
+#define                AR9170_MAC_VIRTUAL_CCA_Q1               BIT(16)
+#define                AR9170_MAC_VIRTUAL_CCA_Q2               BIT(17)
+#define                AR9170_MAC_VIRTUAL_CCA_Q3               BIT(18)
+#define                AR9170_MAC_VIRTUAL_CCA_Q4               BIT(19)
+#define                AR9170_MAC_VIRTUAL_CCA_ALL              (0xf8000)
+
+#define        AR9170_MAC_REG_AC1_AC0_TXOP             (AR9170_MAC_REG_BASE + 0xb44)
+#define        AR9170_MAC_REG_AC3_AC2_TXOP             (AR9170_MAC_REG_BASE + 0xb48)
+
+#define        AR9170_MAC_REG_AMPDU_COUNT              (AR9170_MAC_REG_BASE + 0xb88)
+#define        AR9170_MAC_REG_MPDU_COUNT               (AR9170_MAC_REG_BASE + 0xb8c)
+
+#define        AR9170_MAC_REG_AMPDU_FACTOR             (AR9170_MAC_REG_BASE + 0xb9c)
+#define                AR9170_MAC_AMPDU_FACTOR                 0x7f0000
+#define                AR9170_MAC_AMPDU_FACTOR_S               16
+#define        AR9170_MAC_REG_AMPDU_DENSITY            (AR9170_MAC_REG_BASE + 0xba0)
+#define                AR9170_MAC_AMPDU_DENSITY                0x7
+#define                AR9170_MAC_AMPDU_DENSITY_S              0
+
+#define        AR9170_MAC_REG_FCS_SELECT               (AR9170_MAC_REG_BASE + 0xbb0)
+#define                AR9170_MAC_FCS_SWFCS                    0x1
+#define                AR9170_MAC_FCS_FIFO_PROT                0x4
+
+#define        AR9170_MAC_REG_RTS_CTS_TPC              (AR9170_MAC_REG_BASE + 0xbb4)
+#define AR9170_MAC_REG_CFEND_QOSNULL_TPC       (AR9170_MAC_REG_BASE + 0xbb8)
+
+#define        AR9170_MAC_REG_ACK_TABLE                (AR9170_MAC_REG_BASE + 0xc00)
+#define AR9170_MAC_REG_RX_CONTROL              (AR9170_MAC_REG_BASE + 0xc40)
+#define                AR9170_MAC_RX_CTRL_DEAGG                0x1
+#define                AR9170_MAC_RX_CTRL_SHORT_FILTER         0x2
+#define                AR9170_MAC_RX_CTRL_SA_DA_SEARCH         0x20
+#define                AR9170_MAC_RX_CTRL_PASS_TO_HOST         BIT(28)
+#define                AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER       BIT(30)
+
+#define AR9170_MAC_REG_RX_CONTROL_1            (AR9170_MAC_REG_BASE + 0xc44)
+
+#define        AR9170_MAC_REG_AMPDU_RX_THRESH          (AR9170_MAC_REG_BASE + 0xc50)
+
+#define        AR9170_MAC_REG_RX_MPDU                  (AR9170_MAC_REG_BASE + 0xca0)
+#define        AR9170_MAC_REG_RX_DROPPED_MPDU          (AR9170_MAC_REG_BASE + 0xca4)
+#define        AR9170_MAC_REG_RX_DEL_MPDU              (AR9170_MAC_REG_BASE + 0xca8)
+#define        AR9170_MAC_REG_RX_PHY_MISC_ERROR        (AR9170_MAC_REG_BASE + 0xcac)
+#define        AR9170_MAC_REG_RX_PHY_XR_ERROR          (AR9170_MAC_REG_BASE + 0xcb0)
+#define        AR9170_MAC_REG_RX_PHY_OFDM_ERROR        (AR9170_MAC_REG_BASE + 0xcb4)
+#define        AR9170_MAC_REG_RX_PHY_CCK_ERROR         (AR9170_MAC_REG_BASE + 0xcb8)
+#define        AR9170_MAC_REG_RX_PHY_HT_ERROR          (AR9170_MAC_REG_BASE + 0xcbc)
+#define        AR9170_MAC_REG_RX_PHY_TOTAL             (AR9170_MAC_REG_BASE + 0xcc0)
+
+#define        AR9170_MAC_REG_DMA_TXQ_ADDR             (AR9170_MAC_REG_BASE + 0xd00)
+#define        AR9170_MAC_REG_DMA_TXQ_CURR_ADDR        (AR9170_MAC_REG_BASE + 0xd04)
+#define        AR9170_MAC_REG_DMA_TXQ0_ADDR            (AR9170_MAC_REG_BASE + 0xd00)
+#define        AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd04)
+#define        AR9170_MAC_REG_DMA_TXQ1_ADDR            (AR9170_MAC_REG_BASE + 0xd08)
+#define        AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd0c)
+#define        AR9170_MAC_REG_DMA_TXQ2_ADDR            (AR9170_MAC_REG_BASE + 0xd10)
+#define        AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd14)
+#define        AR9170_MAC_REG_DMA_TXQ3_ADDR            (AR9170_MAC_REG_BASE + 0xd18)
+#define        AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd1c)
+#define        AR9170_MAC_REG_DMA_TXQ4_ADDR            (AR9170_MAC_REG_BASE + 0xd20)
+#define        AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR       (AR9170_MAC_REG_BASE + 0xd24)
+#define        AR9170_MAC_REG_DMA_RXQ_ADDR             (AR9170_MAC_REG_BASE + 0xd28)
+#define        AR9170_MAC_REG_DMA_RXQ_CURR_ADDR        (AR9170_MAC_REG_BASE + 0xd2c)
+
+#define        AR9170_MAC_REG_DMA_TRIGGER              (AR9170_MAC_REG_BASE + 0xd30)
+#define                AR9170_DMA_TRIGGER_TXQ0                 BIT(0)
+#define                AR9170_DMA_TRIGGER_TXQ1                 BIT(1)
+#define                AR9170_DMA_TRIGGER_TXQ2                 BIT(2)
+#define                AR9170_DMA_TRIGGER_TXQ3                 BIT(3)
+#define                AR9170_DMA_TRIGGER_TXQ4                 BIT(4)
+#define                AR9170_DMA_TRIGGER_RXQ                  BIT(8)
+
+#define AR9170_MAC_REG_DMA_WLAN_STATUS         (AR9170_MAC_REG_BASE + 0xd38)
+#define        AR9170_MAC_REG_DMA_STATUS               (AR9170_MAC_REG_BASE + 0xd3c)
+
+#define        AR9170_MAC_REG_TXRX_MPI                 (AR9170_MAC_REG_BASE + 0xd7c)
+#define                AR9170_MAC_TXRX_MPI_TX_MPI_MASK         0x0000000f
+#define                AR9170_MAC_TXRX_MPI_TX_TO_MASK          0x0000fff0
+#define                AR9170_MAC_TXRX_MPI_RX_MPI_MASK         0x000f0000
+#define                AR9170_MAC_TXRX_MPI_RX_TO_MASK          0xfff00000
+
+#define        AR9170_MAC_REG_BCN_ADDR                 (AR9170_MAC_REG_BASE + 0xd84)
+#define        AR9170_MAC_REG_BCN_LENGTH               (AR9170_MAC_REG_BASE + 0xd88)
+#define                AR9170_MAC_BCN_LENGTH_MAX               256
+
+#define AR9170_MAC_REG_BCN_STATUS              (AR9170_MAC_REG_BASE + 0xd8c)
+
+#define        AR9170_MAC_REG_BCN_PLCP                 (AR9170_MAC_REG_BASE + 0xd90)
+#define        AR9170_MAC_REG_BCN_CTRL                 (AR9170_MAC_REG_BASE + 0xd94)
+#define                AR9170_BCN_CTRL_READY                   0x01
+#define                AR9170_BCN_CTRL_LOCK                    0x02
+
+#define AR9170_MAC_REG_BCN_CURR_ADDR           (AR9170_MAC_REG_BASE + 0xd98)
+#define        AR9170_MAC_REG_BCN_COUNT                (AR9170_MAC_REG_BASE + 0xd9c)
+
+
+#define        AR9170_MAC_REG_BCN_HT1                  (AR9170_MAC_REG_BASE + 0xda0)
+#define        AR9170_MAC_REG_BCN_HT2                  (AR9170_MAC_REG_BASE + 0xda4)
+
+#define        AR9170_MAC_REG_DMA_TXQX_ADDR_CURR       (AR9170_MAC_REG_BASE + 0xdc0)
+
+/* Random number generator */
+#define        AR9170_RAND_REG_BASE                    0x1d0000
+
+#define        AR9170_RAND_REG_NUM                     (AR9170_RAND_REG_BASE + 0x000)
+#define        AR9170_RAND_REG_MODE                    (AR9170_RAND_REG_BASE + 0x004)
+#define                AR9170_RAND_MODE_MANUAL                 0x000
+#define                AR9170_RAND_MODE_FREE                   0x001
+
+/* GPIO */
+#define        AR9170_GPIO_REG_BASE                    0x1d0100
+#define        AR9170_GPIO_REG_PORT_TYPE               (AR9170_GPIO_REG_BASE + 0x000)
+#define        AR9170_GPIO_REG_PORT_DATA               (AR9170_GPIO_REG_BASE + 0x004)
+#define                AR9170_GPIO_PORT_LED_0                  1
+#define                AR9170_GPIO_PORT_LED_1                  2
+/* WPS Button GPIO for TP-Link TL-WN821N */
+#define                AR9170_GPIO_PORT_WPS_BUTTON_PRESSED     4
+
+/* Memory Controller */
+#define        AR9170_MC_REG_BASE                      0x1d1000
+
+#define        AR9170_MC_REG_FLASH_WAIT_STATE          (AR9170_MC_REG_BASE + 0x000)
+#define        AR9170_MC_REG_SEEPROM_WP0               (AR9170_MC_REG_BASE + 0x400)
+#define        AR9170_MC_REG_SEEPROM_WP1               (AR9170_MC_REG_BASE + 0x404)
+#define        AR9170_MC_REG_SEEPROM_WP2               (AR9170_MC_REG_BASE + 0x408)
+
+/* Interrupt Controller */
+#define        AR9170_MAX_INT_SRC                      9
+#define        AR9170_INT_REG_BASE                     0x1d2000
+
+#define        AR9170_INT_REG_FLAG                     (AR9170_INT_REG_BASE + 0x000)
+#define        AR9170_INT_REG_FIQ_MASK                 (AR9170_INT_REG_BASE + 0x004)
+#define        AR9170_INT_REG_IRQ_MASK                 (AR9170_INT_REG_BASE + 0x008)
+/* INT_REG_FLAG, INT_REG_FIQ_MASK and INT_REG_IRQ_MASK */
+#define                AR9170_INT_FLAG_WLAN                    0x001
+#define                AR9170_INT_FLAG_PTAB_BIT                0x002
+#define                AR9170_INT_FLAG_SE_BIT                  0x004
+#define                AR9170_INT_FLAG_UART_BIT                0x008
+#define                AR9170_INT_FLAG_TIMER_BIT               0x010
+#define                AR9170_INT_FLAG_EXT_BIT                 0x020
+#define                AR9170_INT_FLAG_SW_BIT                  0x040
+#define                AR9170_INT_FLAG_USB_BIT                 0x080
+#define                AR9170_INT_FLAG_ETHERNET_BIT            0x100
+
+#define        AR9170_INT_REG_PRIORITY1                (AR9170_INT_REG_BASE + 0x00c)
+#define        AR9170_INT_REG_PRIORITY2                (AR9170_INT_REG_BASE + 0x010)
+#define        AR9170_INT_REG_PRIORITY3                (AR9170_INT_REG_BASE + 0x014)
+#define        AR9170_INT_REG_EXT_INT_CONTROL          (AR9170_INT_REG_BASE + 0x018)
+#define        AR9170_INT_REG_SW_INT_CONTROL           (AR9170_INT_REG_BASE + 0x01c)
+#define                AR9170_INT_SW_INT_ENABLE                0x1
+
+#define        AR9170_INT_REG_FIQ_ENCODE               (AR9170_INT_REG_BASE + 0x020)
+#define        AR9170_INT_INT_IRQ_ENCODE               (AR9170_INT_REG_BASE + 0x024)
+
+/* Power Management */
+#define        AR9170_PWR_REG_BASE                     0x1d4000
+
+#define AR9170_PWR_REG_POWER_STATE             (AR9170_PWR_REG_BASE + 0x000)
+
+#define        AR9170_PWR_REG_RESET                    (AR9170_PWR_REG_BASE + 0x004)
+#define                AR9170_PWR_RESET_COMMIT_RESET_MASK      BIT(0)
+#define                AR9170_PWR_RESET_WLAN_MASK              BIT(1)
+#define                AR9170_PWR_RESET_DMA_MASK               BIT(2)
+#define                AR9170_PWR_RESET_BRIDGE_MASK            BIT(3)
+#define                AR9170_PWR_RESET_AHB_MASK               BIT(9)
+#define                AR9170_PWR_RESET_BB_WARM_RESET          BIT(10)
+#define                AR9170_PWR_RESET_BB_COLD_RESET          BIT(11)
+#define                AR9170_PWR_RESET_ADDA_CLK_COLD_RESET    BIT(12)
+#define                AR9170_PWR_RESET_PLL                    BIT(13)
+#define                AR9170_PWR_RESET_USB_PLL                BIT(14)
+
+#define        AR9170_PWR_REG_CLOCK_SEL                (AR9170_PWR_REG_BASE + 0x008)
+#define                AR9170_PWR_CLK_AHB_40MHZ                0
+#define                AR9170_PWR_CLK_AHB_20_22MHZ             1
+#define                AR9170_PWR_CLK_AHB_40_44MHZ             2
+#define                AR9170_PWR_CLK_AHB_80_88MHZ             3
+#define                AR9170_PWR_CLK_DAC_160_INV_DLY          0x70
+
+#define        AR9170_PWR_REG_CHIP_REVISION            (AR9170_PWR_REG_BASE + 0x010)
+#define AR9170_PWR_REG_PLL_ADDAC               (AR9170_PWR_REG_BASE + 0x014)
+#define        AR9170_PWR_REG_WATCH_DOG_MAGIC          (AR9170_PWR_REG_BASE + 0x020)
+
+/* Faraday USB Controller */
+#define        AR9170_USB_REG_BASE                     0x1e1000
+
+#define        AR9170_USB_REG_MAIN_CTRL                (AR9170_USB_REG_BASE + 0x000)
+#define                AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP      BIT(0)
+#define                AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT  BIT(2)
+#define                AR9170_USB_MAIN_CTRL_HIGHSPEED          BIT(6)
+
+#define        AR9170_USB_REG_DEVICE_ADDRESS           (AR9170_USB_REG_BASE + 0x001)
+#define                AR9170_USB_DEVICE_ADDRESS_CONFIGURE     BIT(7)
+
+#define        AR9170_USB_REG_TEST                     (AR9170_USB_REG_BASE + 0x002)
+#define        AR9170_USB_REG_PHY_TEST_SELECT          (AR9170_USB_REG_BASE + 0x008)
+#define        AR9170_USB_REG_CX_CONFIG_STATUS         (AR9170_USB_REG_BASE + 0x00b)
+#define        AR9170_USB_REG_EP0_DATA                 (AR9170_USB_REG_BASE + 0x00c)
+#define        AR9170_USB_REG_EP0_DATA1                (AR9170_USB_REG_BASE + 0x00c)
+#define        AR9170_USB_REG_EP0_DATA2                (AR9170_USB_REG_BASE + 0x00d)
+
+#define        AR9170_USB_REG_INTR_MASK_BYTE_0         (AR9170_USB_REG_BASE + 0x011)
+#define        AR9170_USB_REG_INTR_MASK_BYTE_1         (AR9170_USB_REG_BASE + 0x012)
+#define        AR9170_USB_REG_INTR_MASK_BYTE_2         (AR9170_USB_REG_BASE + 0x013)
+#define        AR9170_USB_REG_INTR_MASK_BYTE_3         (AR9170_USB_REG_BASE + 0x014)
+#define        AR9170_USB_REG_INTR_MASK_BYTE_4         (AR9170_USB_REG_BASE + 0x015)
+#define                AR9170_USB_INTR_DISABLE_OUT_INT         (BIT(7) | BIT(6))
+
+#define        AR9170_USB_REG_INTR_MASK_BYTE_5         (AR9170_USB_REG_BASE + 0x016)
+#define        AR9170_USB_REG_INTR_MASK_BYTE_6         (AR9170_USB_REG_BASE + 0x017)
+#define                AR9170_USB_INTR_DISABLE_IN_INT          BIT(6)
+
+#define        AR9170_USB_REG_INTR_MASK_BYTE_7         (AR9170_USB_REG_BASE + 0x018)
+
+#define        AR9170_USB_REG_INTR_GROUP               (AR9170_USB_REG_BASE + 0x020)
+
+#define        AR9170_USB_REG_INTR_SOURCE_0            (AR9170_USB_REG_BASE + 0x021)
+#define        AR9170_USB_REG_INTR_SOURCE_1            (AR9170_USB_REG_BASE + 0x022)
+#define        AR9170_USB_REG_INTR_SOURCE_2            (AR9170_USB_REG_BASE + 0x023)
+#define        AR9170_USB_REG_INTR_SOURCE_3            (AR9170_USB_REG_BASE + 0x024)
+#define        AR9170_USB_REG_INTR_SOURCE_4            (AR9170_USB_REG_BASE + 0x025)
+#define        AR9170_USB_REG_INTR_SOURCE_5            (AR9170_USB_REG_BASE + 0x026)
+#define        AR9170_USB_REG_INTR_SOURCE_6            (AR9170_USB_REG_BASE + 0x027)
+#define        AR9170_USB_REG_INTR_SOURCE_7            (AR9170_USB_REG_BASE + 0x028)
+
+#define        AR9170_USB_REG_EP_MAP                   (AR9170_USB_REG_BASE + 0x030)
+#define        AR9170_USB_REG_EP1_MAP                  (AR9170_USB_REG_BASE + 0x030)
+#define        AR9170_USB_REG_EP2_MAP                  (AR9170_USB_REG_BASE + 0x031)
+#define        AR9170_USB_REG_EP3_MAP                  (AR9170_USB_REG_BASE + 0x032)
+#define        AR9170_USB_REG_EP4_MAP                  (AR9170_USB_REG_BASE + 0x033)
+#define        AR9170_USB_REG_EP5_MAP                  (AR9170_USB_REG_BASE + 0x034)
+#define        AR9170_USB_REG_EP6_MAP                  (AR9170_USB_REG_BASE + 0x035)
+#define        AR9170_USB_REG_EP7_MAP                  (AR9170_USB_REG_BASE + 0x036)
+#define        AR9170_USB_REG_EP8_MAP                  (AR9170_USB_REG_BASE + 0x037)
+#define        AR9170_USB_REG_EP9_MAP                  (AR9170_USB_REG_BASE + 0x038)
+#define        AR9170_USB_REG_EP10_MAP                 (AR9170_USB_REG_BASE + 0x039)
+
+#define        AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH      (AR9170_USB_REG_BASE + 0x03f)
+#define                AR9170_USB_EP_IN_TOGGLE                 0x10
+
+#define        AR9170_USB_REG_EP_IN_MAX_SIZE_LOW       (AR9170_USB_REG_BASE + 0x03e)
+
+#define        AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH     (AR9170_USB_REG_BASE + 0x05f)
+#define                AR9170_USB_EP_OUT_TOGGLE                0x10
+
+#define        AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW      (AR9170_USB_REG_BASE + 0x05e)
+
+#define        AR9170_USB_REG_EP3_BYTE_COUNT_HIGH      (AR9170_USB_REG_BASE + 0x0ae)
+#define        AR9170_USB_REG_EP3_BYTE_COUNT_LOW       (AR9170_USB_REG_BASE + 0x0be)
+#define        AR9170_USB_REG_EP4_BYTE_COUNT_HIGH      (AR9170_USB_REG_BASE + 0x0af)
+#define        AR9170_USB_REG_EP4_BYTE_COUNT_LOW       (AR9170_USB_REG_BASE + 0x0bf)
+
+#define        AR9170_USB_REG_FIFO_MAP                 (AR9170_USB_REG_BASE + 0x080)
+#define        AR9170_USB_REG_FIFO0_MAP                (AR9170_USB_REG_BASE + 0x080)
+#define        AR9170_USB_REG_FIFO1_MAP                (AR9170_USB_REG_BASE + 0x081)
+#define        AR9170_USB_REG_FIFO2_MAP                (AR9170_USB_REG_BASE + 0x082)
+#define        AR9170_USB_REG_FIFO3_MAP                (AR9170_USB_REG_BASE + 0x083)
+#define        AR9170_USB_REG_FIFO4_MAP                (AR9170_USB_REG_BASE + 0x084)
+#define        AR9170_USB_REG_FIFO5_MAP                (AR9170_USB_REG_BASE + 0x085)
+#define        AR9170_USB_REG_FIFO6_MAP                (AR9170_USB_REG_BASE + 0x086)
+#define        AR9170_USB_REG_FIFO7_MAP                (AR9170_USB_REG_BASE + 0x087)
+#define        AR9170_USB_REG_FIFO8_MAP                (AR9170_USB_REG_BASE + 0x088)
+#define        AR9170_USB_REG_FIFO9_MAP                (AR9170_USB_REG_BASE + 0x089)
+
+#define        AR9170_USB_REG_FIFO_CONFIG              (AR9170_USB_REG_BASE + 0x090)
+#define        AR9170_USB_REG_FIFO0_CONFIG             (AR9170_USB_REG_BASE + 0x090)
+#define        AR9170_USB_REG_FIFO1_CONFIG             (AR9170_USB_REG_BASE + 0x091)
+#define        AR9170_USB_REG_FIFO2_CONFIG             (AR9170_USB_REG_BASE + 0x092)
+#define        AR9170_USB_REG_FIFO3_CONFIG             (AR9170_USB_REG_BASE + 0x093)
+#define        AR9170_USB_REG_FIFO4_CONFIG             (AR9170_USB_REG_BASE + 0x094)
+#define        AR9170_USB_REG_FIFO5_CONFIG             (AR9170_USB_REG_BASE + 0x095)
+#define        AR9170_USB_REG_FIFO6_CONFIG             (AR9170_USB_REG_BASE + 0x096)
+#define        AR9170_USB_REG_FIFO7_CONFIG             (AR9170_USB_REG_BASE + 0x097)
+#define        AR9170_USB_REG_FIFO8_CONFIG             (AR9170_USB_REG_BASE + 0x098)
+#define        AR9170_USB_REG_FIFO9_CONFIG             (AR9170_USB_REG_BASE + 0x099)
+
+#define        AR9170_USB_REG_EP3_DATA                 (AR9170_USB_REG_BASE + 0x0f8)
+#define        AR9170_USB_REG_EP4_DATA                 (AR9170_USB_REG_BASE + 0x0fc)
+
+#define        AR9170_USB_REG_FIFO_SIZE                (AR9170_USB_REG_BASE + 0x100)
+#define        AR9170_USB_REG_DMA_CTL                  (AR9170_USB_REG_BASE + 0x108)
+#define                AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE     BIT(0)
+#define                AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE   BIT(1)
+#define                AR9170_USB_DMA_CTL_HIGH_SPEED           BIT(2)
+#define                AR9170_USB_DMA_CTL_UP_PACKET_MODE       BIT(3)
+#define                AR9170_USB_DMA_CTL_UP_STREAM_S          4
+#define                AR9170_USB_DMA_CTL_UP_STREAM            (BIT(4) | BIT(5))
+#define                AR9170_USB_DMA_CTL_UP_STREAM_4K         (0)
+#define                AR9170_USB_DMA_CTL_UP_STREAM_8K         BIT(4)
+#define                AR9170_USB_DMA_CTL_UP_STREAM_16K        BIT(5)
+#define                AR9170_USB_DMA_CTL_UP_STREAM_32K        (BIT(4) | BIT(5))
+#define                AR9170_USB_DMA_CTL_DOWN_STREAM          BIT(6)
+
+#define        AR9170_USB_REG_DMA_STATUS               (AR9170_USB_REG_BASE + 0x10c)
+#define                AR9170_USB_DMA_STATUS_UP_IDLE           BIT(8)
+#define                AR9170_USB_DMA_STATUS_DN_IDLE           BIT(16)
+
+#define        AR9170_USB_REG_MAX_AGG_UPLOAD           (AR9170_USB_REG_BASE + 0x110)
+#define        AR9170_USB_REG_UPLOAD_TIME_CTL          (AR9170_USB_REG_BASE + 0x114)
+#define        AR9170_USB_REG_CBUS_CTRL                (AR9170_USB_REG_BASE + 0x1f0)
+#define                AR9170_USB_CBUS_CTRL_BUFFER_END         (BIT(1))
+
+/* PCI/USB to AHB Bridge */
+#define        AR9170_PTA_REG_BASE                     0x1e2000
+
+#define        AR9170_PTA_REG_CMD                      (AR9170_PTA_REG_BASE + 0x000)
+#define        AR9170_PTA_REG_PARAM1                   (AR9170_PTA_REG_BASE + 0x004)
+#define        AR9170_PTA_REG_PARAM2                   (AR9170_PTA_REG_BASE + 0x008)
+#define        AR9170_PTA_REG_PARAM3                   (AR9170_PTA_REG_BASE + 0x00c)
+#define        AR9170_PTA_REG_RSP                      (AR9170_PTA_REG_BASE + 0x010)
+#define        AR9170_PTA_REG_STATUS1                  (AR9170_PTA_REG_BASE + 0x014)
+#define        AR9170_PTA_REG_STATUS2                  (AR9170_PTA_REG_BASE + 0x018)
+#define        AR9170_PTA_REG_STATUS3                  (AR9170_PTA_REG_BASE + 0x01c)
+#define        AR9170_PTA_REG_AHB_INT_FLAG             (AR9170_PTA_REG_BASE + 0x020)
+#define        AR9170_PTA_REG_AHB_INT_MASK             (AR9170_PTA_REG_BASE + 0x024)
+#define        AR9170_PTA_REG_AHB_INT_ACK              (AR9170_PTA_REG_BASE + 0x028)
+#define        AR9170_PTA_REG_AHB_SCRATCH1             (AR9170_PTA_REG_BASE + 0x030)
+#define        AR9170_PTA_REG_AHB_SCRATCH2             (AR9170_PTA_REG_BASE + 0x034)
+#define        AR9170_PTA_REG_AHB_SCRATCH3             (AR9170_PTA_REG_BASE + 0x038)
+#define        AR9170_PTA_REG_AHB_SCRATCH4             (AR9170_PTA_REG_BASE + 0x03c)
+
+#define        AR9170_PTA_REG_SHARE_MEM_CTRL           (AR9170_PTA_REG_BASE + 0x124)
+
+/*
+ * PCI to AHB Bridge
+ */
+
+#define        AR9170_PTA_REG_INT_FLAG                 (AR9170_PTA_REG_BASE + 0x100)
+#define                AR9170_PTA_INT_FLAG_DN                  0x01
+#define                AR9170_PTA_INT_FLAG_UP                  0x02
+#define                AR9170_PTA_INT_FLAG_CMD                 0x04
+
+#define        AR9170_PTA_REG_INT_MASK                 (AR9170_PTA_REG_BASE + 0x104)
+#define        AR9170_PTA_REG_DN_DMA_ADDRL             (AR9170_PTA_REG_BASE + 0x108)
+#define        AR9170_PTA_REG_DN_DMA_ADDRH             (AR9170_PTA_REG_BASE + 0x10c)
+#define        AR9170_PTA_REG_UP_DMA_ADDRL             (AR9170_PTA_REG_BASE + 0x110)
+#define        AR9170_PTA_REG_UP_DMA_ADDRH             (AR9170_PTA_REG_BASE + 0x114)
+#define        AR9170_PTA_REG_DN_PEND_TIME             (AR9170_PTA_REG_BASE + 0x118)
+#define        AR9170_PTA_REG_UP_PEND_TIME             (AR9170_PTA_REG_BASE + 0x11c)
+#define        AR9170_PTA_REG_CONTROL                  (AR9170_PTA_REG_BASE + 0x120)
+#define                AR9170_PTA_CTRL_4_BEAT_BURST            0x00
+#define                AR9170_PTA_CTRL_8_BEAT_BURST            0x01
+#define                AR9170_PTA_CTRL_16_BEAT_BURST           0x02
+#define                AR9170_PTA_CTRL_LOOPBACK_MODE           0x10
+
+#define        AR9170_PTA_REG_MEM_CTRL                 (AR9170_PTA_REG_BASE + 0x124)
+#define        AR9170_PTA_REG_MEM_ADDR                 (AR9170_PTA_REG_BASE + 0x128)
+#define        AR9170_PTA_REG_DN_DMA_TRIGGER           (AR9170_PTA_REG_BASE + 0x12c)
+#define        AR9170_PTA_REG_UP_DMA_TRIGGER           (AR9170_PTA_REG_BASE + 0x130)
+#define        AR9170_PTA_REG_DMA_STATUS               (AR9170_PTA_REG_BASE + 0x134)
+#define        AR9170_PTA_REG_DN_CURR_ADDRL            (AR9170_PTA_REG_BASE + 0x138)
+#define        AR9170_PTA_REG_DN_CURR_ADDRH            (AR9170_PTA_REG_BASE + 0x13c)
+#define        AR9170_PTA_REG_UP_CURR_ADDRL            (AR9170_PTA_REG_BASE + 0x140)
+#define        AR9170_PTA_REG_UP_CURR_ADDRH            (AR9170_PTA_REG_BASE + 0x144)
+#define        AR9170_PTA_REG_DMA_MODE_CTRL            (AR9170_PTA_REG_BASE + 0x148)
+#define                AR9170_PTA_DMA_MODE_CTRL_RESET          BIT(0)
+#define                AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB    BIT(1)
+
+/* Protocol Controller Module */
+#define        AR9170_MAC_REG_PC_REG_BASE              (AR9170_MAC_REG_BASE + 0xe00)
+
+
+#define        AR9170_NUM_LEDS                         2
+
+/* CAM */
+#define        AR9170_CAM_MAX_USER                     64
+#define        AR9170_CAM_MAX_KEY_LENGTH               16
+
+#define AR9170_SRAM_OFFSET             0x100000
+#define AR9170_SRAM_SIZE               0x18000
+
+#define AR9170_PRAM_OFFSET             0x200000
+#define AR9170_PRAM_SIZE               0x8000
+
+enum cpu_clock {
+       AHB_STATIC_40MHZ = 0,
+       AHB_GMODE_22MHZ = 1,
+       AHB_AMODE_20MHZ = 1,
+       AHB_GMODE_44MHZ = 2,
+       AHB_AMODE_40MHZ = 2,
+       AHB_GMODE_88MHZ = 3,
+       AHB_AMODE_80MHZ = 3
+};
+
+/* USB endpoints */
+enum ar9170_usb_ep {
+       /*
+        * Control EP is always EP 0 (USB SPEC)
+        *
+        * The weird thing is: the original firmware has a few
+        * comments that suggest that the actual EP numbers
+        * are in the 1 to 10 range?!
+        */
+       AR9170_USB_EP_CTRL              = 0,
+
+       AR9170_USB_EP_TX,
+       AR9170_USB_EP_RX,
+       AR9170_USB_EP_IRQ,
+       AR9170_USB_EP_CMD,
+       AR9170_USB_NUM_EXTRA_EP         = 4,
+
+       __AR9170_USB_NUM_EP,
+
+       __AR9170_USB_NUM_MAX_EP         = 10
+};
+
+enum ar9170_usb_fifo {
+       __AR9170_USB_NUM_MAX_FIFO       = 10
+};
+
+enum ar9170_tx_queues {
+       AR9170_TXQ0     = 0,
+       AR9170_TXQ1,
+       AR9170_TXQ2,
+       AR9170_TXQ3,
+       AR9170_TXQ_SPECIAL,
+
+       /* keep last */
+       __AR9170_NUM_TX_QUEUES = 5
+};
+
+#define        AR9170_TX_STREAM_TAG            0x697e
+#define        AR9170_RX_STREAM_TAG            0x4e00
+#define        AR9170_RX_STREAM_MAX_SIZE       0xffff
+
+struct ar9170_stream {
+       __le16 length;
+       __le16 tag;
+
+       u8 payload[0];
+};
+
+#define AR9170_MAX_ACKTABLE_ENTRIES                    8
+#define AR9170_MAX_VIRTUAL_MAC                         7
+
+#define        AR9170_USB_EP_CTRL_MAX                          64
+#define        AR9170_USB_EP_TX_MAX                            512
+#define        AR9170_USB_EP_RX_MAX                            512
+#define        AR9170_USB_EP_IRQ_MAX                           64
+#define        AR9170_USB_EP_CMD_MAX                           64
+
+/* Trigger PRETBTT interrupt 6 Kus earlier */
+#define CARL9170_PRETBTT_KUS                           6
+
+#define        AR5416_MAX_RATE_POWER                           63
+
+#define SET_VAL(reg, value, newvalue)                                  \
+       (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
+
+#define MOD_VAL(reg, value, newvalue)                                  \
+       (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
+#endif /* __CARL9170_SHARED_HW_H */
diff --git a/drivers/net/wireless/ath/carl9170/phy.h b/drivers/net/wireless/ath/carl9170/phy.h
new file mode 100644 (file)
index 0000000..53c18d3
--- /dev/null
@@ -0,0 +1,567 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * PHY register map
+ *
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_PHY_H
+#define __CARL9170_SHARED_PHY_H
+
+#define        AR9170_PHY_REG_BASE                     (0x1bc000 + 0x9800)
+#define        AR9170_PHY_REG(_n)                      (AR9170_PHY_REG_BASE + \
+                                                ((_n) << 2))
+
+#define        AR9170_PHY_REG_TEST                     (AR9170_PHY_REG_BASE + 0x0000)
+#define                AR9170_PHY_TEST_AGC_CLR                 0x10000000
+#define                AR9170_PHY_TEST_RFSILENT_BB             0x00002000
+
+#define        AR9170_PHY_REG_TURBO                    (AR9170_PHY_REG_BASE + 0x0004)
+#define                AR9170_PHY_TURBO_FC_TURBO_MODE          0x00000001
+#define                AR9170_PHY_TURBO_FC_TURBO_SHORT         0x00000002
+#define                AR9170_PHY_TURBO_FC_DYN2040_EN          0x00000004
+#define                AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY    0x00000008
+#define                AR9170_PHY_TURBO_FC_DYN2040_PRI_CH      0x00000010
+/* For 25 MHz channel spacing -- not used but supported by hw */
+#define                AR9170_PHY_TURBO_FC_DYN2040_EXT_CH      0x00000020
+#define                AR9170_PHY_TURBO_FC_HT_EN               0x00000040
+#define                AR9170_PHY_TURBO_FC_SHORT_GI_40         0x00000080
+#define                AR9170_PHY_TURBO_FC_WALSH               0x00000100
+#define                AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1      0x00000200
+#define                AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO     0x00000800
+
+#define        AR9170_PHY_REG_TEST2                    (AR9170_PHY_REG_BASE + 0x0008)
+
+#define        AR9170_PHY_REG_TIMING2                  (AR9170_PHY_REG_BASE + 0x0010)
+#define                AR9170_PHY_TIMING2_USE_FORCE            0x00001000
+#define                AR9170_PHY_TIMING2_FORCE                0x00000fff
+#define                AR9170_PHY_TIMING2_FORCE_S                       0
+
+#define        AR9170_PHY_REG_TIMING3                  (AR9170_PHY_REG_BASE + 0x0014)
+#define                AR9170_PHY_TIMING3_DSC_EXP              0x0001e000
+#define                AR9170_PHY_TIMING3_DSC_EXP_S            13
+#define                AR9170_PHY_TIMING3_DSC_MAN              0xfffe0000
+#define                AR9170_PHY_TIMING3_DSC_MAN_S            17
+
+#define        AR9170_PHY_REG_CHIP_ID                  (AR9170_PHY_REG_BASE + 0x0018)
+#define                AR9170_PHY_CHIP_ID_REV_0                0x80
+#define                AR9170_PHY_CHIP_ID_REV_1                0x81
+#define                AR9170_PHY_CHIP_ID_9160_REV_0           0xb0
+
+#define        AR9170_PHY_REG_ACTIVE                   (AR9170_PHY_REG_BASE + 0x001c)
+#define                AR9170_PHY_ACTIVE_EN                    0x00000001
+#define                AR9170_PHY_ACTIVE_DIS                   0x00000000
+
+#define        AR9170_PHY_REG_RF_CTL2                  (AR9170_PHY_REG_BASE + 0x0024)
+#define                AR9170_PHY_RF_CTL2_TX_END_DATA_START    0x000000ff
+#define                AR9170_PHY_RF_CTL2_TX_END_DATA_START_S  0
+#define                AR9170_PHY_RF_CTL2_TX_END_PA_ON         0x0000ff00
+#define                AR9170_PHY_RF_CTL2_TX_END_PA_ON_S       8
+
+#define        AR9170_PHY_REG_RF_CTL3                  (AR9170_PHY_REG_BASE + 0x0028)
+#define                AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON   0x00ff0000
+#define                AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16
+
+#define        AR9170_PHY_REG_ADC_CTL                  (AR9170_PHY_REG_BASE + 0x002c)
+#define                AR9170_PHY_ADC_CTL_OFF_INBUFGAIN        0x00000003
+#define                AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S      0
+#define                AR9170_PHY_ADC_CTL_OFF_PWDDAC           0x00002000
+#define                AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP       0x00004000
+#define                AR9170_PHY_ADC_CTL_OFF_PWDADC           0x00008000
+#define                AR9170_PHY_ADC_CTL_ON_INBUFGAIN         0x00030000
+#define                AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S       16
+
+#define        AR9170_PHY_REG_ADC_SERIAL_CTL           (AR9170_PHY_REG_BASE + 0x0030)
+#define                AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC  0x00000000
+#define                AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO  0x00000001
+
+#define        AR9170_PHY_REG_RF_CTL4                  (AR9170_PHY_REG_BASE + 0x0034)
+#define                AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF      0xff000000
+#define                AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S    24
+#define                AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF      0x00ff0000
+#define                AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S    16
+#define                AR9170_PHY_RF_CTL4_FRAME_XPAB_ON        0x0000ff00
+#define                AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S      8
+#define                AR9170_PHY_RF_CTL4_FRAME_XPAA_ON        0x000000ff
+#define                AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S      0
+
+#define        AR9170_PHY_REG_TSTDAC_CONST             (AR9170_PHY_REG_BASE + 0x003c)
+
+#define        AR9170_PHY_REG_SETTLING                 (AR9170_PHY_REG_BASE + 0x0044)
+#define                AR9170_PHY_SETTLING_SWITCH              0x00003f80
+#define                AR9170_PHY_SETTLING_SWITCH_S            7
+
+#define        AR9170_PHY_REG_RXGAIN                   (AR9170_PHY_REG_BASE + 0x0048)
+#define        AR9170_PHY_REG_RXGAIN_CHAIN_2           (AR9170_PHY_REG_BASE + 0x2048)
+#define                AR9170_PHY_RXGAIN_TXRX_ATTEN            0x0003f000
+#define                AR9170_PHY_RXGAIN_TXRX_ATTEN_S          12
+#define                AR9170_PHY_RXGAIN_TXRX_RF_MAX           0x007c0000
+#define                AR9170_PHY_RXGAIN_TXRX_RF_MAX_S         18
+
+#define        AR9170_PHY_REG_DESIRED_SZ               (AR9170_PHY_REG_BASE + 0x0050)
+#define                AR9170_PHY_DESIRED_SZ_ADC               0x000000ff
+#define                AR9170_PHY_DESIRED_SZ_ADC_S             0
+#define                AR9170_PHY_DESIRED_SZ_PGA               0x0000ff00
+#define                AR9170_PHY_DESIRED_SZ_PGA_S             8
+#define                AR9170_PHY_DESIRED_SZ_TOT_DES           0x0ff00000
+#define                AR9170_PHY_DESIRED_SZ_TOT_DES_S         20
+
+#define        AR9170_PHY_REG_FIND_SIG                 (AR9170_PHY_REG_BASE + 0x0058)
+#define                AR9170_PHY_FIND_SIG_FIRSTEP             0x0003f000
+#define                AR9170_PHY_FIND_SIG_FIRSTEP_S           12
+#define                AR9170_PHY_FIND_SIG_FIRPWR              0x03fc0000
+#define                AR9170_PHY_FIND_SIG_FIRPWR_S            18
+
+#define        AR9170_PHY_REG_AGC_CTL1                 (AR9170_PHY_REG_BASE + 0x005c)
+#define                AR9170_PHY_AGC_CTL1_COARSE_LOW          0x00007f80
+#define                AR9170_PHY_AGC_CTL1_COARSE_LOW_S        7
+#define                AR9170_PHY_AGC_CTL1_COARSE_HIGH         0x003f8000
+#define                AR9170_PHY_AGC_CTL1_COARSE_HIGH_S       15
+
+#define        AR9170_PHY_REG_AGC_CONTROL              (AR9170_PHY_REG_BASE + 0x0060)
+#define                AR9170_PHY_AGC_CONTROL_CAL              0x00000001
+#define                AR9170_PHY_AGC_CONTROL_NF               0x00000002
+#define                AR9170_PHY_AGC_CONTROL_ENABLE_NF        0x00008000
+#define                AR9170_PHY_AGC_CONTROL_FLTR_CAL         0x00010000
+#define                AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF     0x00020000
+
+#define        AR9170_PHY_REG_CCA                      (AR9170_PHY_REG_BASE + 0x0064)
+#define                AR9170_PHY_CCA_MINCCA_PWR               0x0ff80000
+#define                AR9170_PHY_CCA_MINCCA_PWR_S             19
+#define                AR9170_PHY_CCA_THRESH62                 0x0007f000
+#define                AR9170_PHY_CCA_THRESH62_S               12
+
+#define        AR9170_PHY_REG_SFCORR                   (AR9170_PHY_REG_BASE + 0x0068)
+#define                AR9170_PHY_SFCORR_M2COUNT_THR           0x0000001f
+#define                AR9170_PHY_SFCORR_M2COUNT_THR_S         0
+#define                AR9170_PHY_SFCORR_M1_THRESH             0x00fe0000
+#define                AR9170_PHY_SFCORR_M1_THRESH_S           17
+#define                AR9170_PHY_SFCORR_M2_THRESH             0x7f000000
+#define                AR9170_PHY_SFCORR_M2_THRESH_S           24
+
+#define        AR9170_PHY_REG_SFCORR_LOW               (AR9170_PHY_REG_BASE + 0x006c)
+#define                AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
+#define                AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW   0x00003f00
+#define                AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
+#define                AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW     0x001fc000
+#define                AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S   14
+#define                AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW     0x0fe00000
+#define                AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S   21
+
+#define        AR9170_PHY_REG_SLEEP_CTR_CONTROL        (AR9170_PHY_REG_BASE + 0x0070)
+#define        AR9170_PHY_REG_SLEEP_CTR_LIMIT          (AR9170_PHY_REG_BASE + 0x0074)
+#define        AR9170_PHY_REG_SLEEP_SCAL               (AR9170_PHY_REG_BASE + 0x0078)
+
+#define        AR9170_PHY_REG_PLL_CTL                  (AR9170_PHY_REG_BASE + 0x007c)
+#define                AR9170_PHY_PLL_CTL_40                   0xaa
+#define                AR9170_PHY_PLL_CTL_40_5413              0x04
+#define                AR9170_PHY_PLL_CTL_44                   0xab
+#define                AR9170_PHY_PLL_CTL_44_2133              0xeb
+#define                AR9170_PHY_PLL_CTL_40_2133              0xea
+
+#define        AR9170_PHY_REG_BIN_MASK_1               (AR9170_PHY_REG_BASE + 0x0100)
+#define        AR9170_PHY_REG_BIN_MASK_2               (AR9170_PHY_REG_BASE + 0x0104)
+#define        AR9170_PHY_REG_BIN_MASK_3               (AR9170_PHY_REG_BASE + 0x0108)
+#define        AR9170_PHY_REG_MASK_CTL                 (AR9170_PHY_REG_BASE + 0x010c)
+
+/* analogue power on time (100ns) */
+#define        AR9170_PHY_REG_RX_DELAY                 (AR9170_PHY_REG_BASE + 0x0114)
+#define        AR9170_PHY_REG_SEARCH_START_DELAY       (AR9170_PHY_REG_BASE + 0x0118)
+#define                AR9170_PHY_RX_DELAY_DELAY               0x00003fff
+
+#define        AR9170_PHY_REG_TIMING_CTRL4(_i)         (AR9170_PHY_REG_BASE + \
+                                               (0x0120 + ((_i) << 12)))
+#define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF         0x01f
+#define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S       0
+#define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF         0x7e0
+#define                AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S       5
+#define                AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE           0x800
+#define                AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX     0xf000
+#define                AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S   12
+#define                AR9170_PHY_TIMING_CTRL4_DO_IQCAL                0x10000
+#define                AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI        0x80000000
+#define                AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER      0x40000000
+#define                AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK        0x20000000
+#define                AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK       0x10000000
+
+#define        AR9170_PHY_REG_TIMING5                  (AR9170_PHY_REG_BASE + 0x0124)
+#define                AR9170_PHY_TIMING5_CYCPWR_THR1          0x000000fe
+#define                AR9170_PHY_TIMING5_CYCPWR_THR1_S        1
+
+#define        AR9170_PHY_REG_POWER_TX_RATE1           (AR9170_PHY_REG_BASE + 0x0134)
+#define        AR9170_PHY_REG_POWER_TX_RATE2           (AR9170_PHY_REG_BASE + 0x0138)
+#define        AR9170_PHY_REG_POWER_TX_RATE_MAX        (AR9170_PHY_REG_BASE + 0x013c)
+#define                AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
+
+#define        AR9170_PHY_REG_FRAME_CTL                (AR9170_PHY_REG_BASE + 0x0144)
+#define                AR9170_PHY_FRAME_CTL_TX_CLIP            0x00000038
+#define                AR9170_PHY_FRAME_CTL_TX_CLIP_S          3
+
+#define        AR9170_PHY_REG_SPUR_REG                 (AR9170_PHY_REG_BASE + 0x014c)
+#define                AR9170_PHY_SPUR_REG_MASK_RATE_CNTL      (0xff << 18)
+#define                AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S    18
+#define                AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM     0x20000
+#define                AR9170_PHY_SPUR_REG_MASK_RATE_SELECT    (0xff << 9)
+#define                AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S  9
+#define                AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI        0x100
+#define                AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH    0x7f
+#define                AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S  0
+
+#define        AR9170_PHY_REG_RADAR_EXT                (AR9170_PHY_REG_BASE + 0x0140)
+#define                AR9170_PHY_RADAR_EXT_ENA                0x00004000
+
+#define        AR9170_PHY_REG_RADAR_0                  (AR9170_PHY_REG_BASE + 0x0154)
+#define                AR9170_PHY_RADAR_0_ENA                  0x00000001
+#define                AR9170_PHY_RADAR_0_FFT_ENA              0x80000000
+/* inband pulse threshold */
+#define                AR9170_PHY_RADAR_0_INBAND               0x0000003e
+#define                AR9170_PHY_RADAR_0_INBAND_S             1
+/* pulse RSSI threshold */
+#define                AR9170_PHY_RADAR_0_PRSSI                0x00000fc0
+#define                AR9170_PHY_RADAR_0_PRSSI_S              6
+/* pulse height threshold */
+#define                AR9170_PHY_RADAR_0_HEIGHT               0x0003f000
+#define                AR9170_PHY_RADAR_0_HEIGHT_S             12
+/* radar RSSI threshold */
+#define                AR9170_PHY_RADAR_0_RRSSI                0x00fc0000
+#define                AR9170_PHY_RADAR_0_RRSSI_S              18
+/* radar firepower threshold */
+#define                AR9170_PHY_RADAR_0_FIRPWR               0x7f000000
+#define                AR9170_PHY_RADAR_0_FIRPWR_S             24
+
+#define        AR9170_PHY_REG_RADAR_1                  (AR9170_PHY_REG_BASE + 0x0158)
+#define                AR9170_PHY_RADAR_1_RELPWR_ENA           0x00800000
+#define                AR9170_PHY_RADAR_1_USE_FIR128           0x00400000
+#define                AR9170_PHY_RADAR_1_RELPWR_THRESH        0x003f0000
+#define                AR9170_PHY_RADAR_1_RELPWR_THRESH_S      16
+#define                AR9170_PHY_RADAR_1_BLOCK_CHECK          0x00008000
+#define                AR9170_PHY_RADAR_1_MAX_RRSSI            0x00004000
+#define                AR9170_PHY_RADAR_1_RELSTEP_CHECK        0x00002000
+#define                AR9170_PHY_RADAR_1_RELSTEP_THRESH       0x00001f00
+#define                AR9170_PHY_RADAR_1_RELSTEP_THRESH_S     8
+#define                AR9170_PHY_RADAR_1_MAXLEN               0x000000ff
+#define                AR9170_PHY_RADAR_1_MAXLEN_S             0
+
+#define        AR9170_PHY_REG_SWITCH_CHAIN_0           (AR9170_PHY_REG_BASE + 0x0160)
+#define        AR9170_PHY_REG_SWITCH_CHAIN_2           (AR9170_PHY_REG_BASE + 0x2160)
+
+#define        AR9170_PHY_REG_SWITCH_COM               (AR9170_PHY_REG_BASE + 0x0164)
+
+#define        AR9170_PHY_REG_CCA_THRESHOLD            (AR9170_PHY_REG_BASE + 0x0168)
+
+#define        AR9170_PHY_REG_SIGMA_DELTA              (AR9170_PHY_REG_BASE + 0x016c)
+#define                AR9170_PHY_SIGMA_DELTA_ADC_SEL          0x00000003
+#define                AR9170_PHY_SIGMA_DELTA_ADC_SEL_S        0
+#define                AR9170_PHY_SIGMA_DELTA_FILT2            0x000000f8
+#define                AR9170_PHY_SIGMA_DELTA_FILT2_S          3
+#define                AR9170_PHY_SIGMA_DELTA_FILT1            0x00001f00
+#define                AR9170_PHY_SIGMA_DELTA_FILT1_S          8
+#define                AR9170_PHY_SIGMA_DELTA_ADC_CLIP         0x01ffe000
+#define                AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S       13
+
+#define        AR9170_PHY_REG_RESTART                  (AR9170_PHY_REG_BASE + 0x0170)
+#define                AR9170_PHY_RESTART_DIV_GC               0x001c0000
+#define                AR9170_PHY_RESTART_DIV_GC_S             18
+
+#define        AR9170_PHY_REG_RFBUS_REQ                (AR9170_PHY_REG_BASE + 0x017c)
+#define                AR9170_PHY_RFBUS_REQ_EN                 0x00000001
+
+#define        AR9170_PHY_REG_TIMING7                  (AR9170_PHY_REG_BASE + 0x0180)
+#define        AR9170_PHY_REG_TIMING8                  (AR9170_PHY_REG_BASE + 0x0184)
+#define                AR9170_PHY_TIMING8_PILOT_MASK_2         0x000fffff
+#define                AR9170_PHY_TIMING8_PILOT_MASK_2_S       0
+
+#define        AR9170_PHY_REG_BIN_MASK2_1              (AR9170_PHY_REG_BASE + 0x0188)
+#define        AR9170_PHY_REG_BIN_MASK2_2              (AR9170_PHY_REG_BASE + 0x018c)
+#define        AR9170_PHY_REG_BIN_MASK2_3              (AR9170_PHY_REG_BASE + 0x0190)
+#define        AR9170_PHY_REG_BIN_MASK2_4              (AR9170_PHY_REG_BASE + 0x0194)
+#define                AR9170_PHY_BIN_MASK2_4_MASK_4           0x00003fff
+#define                AR9170_PHY_BIN_MASK2_4_MASK_4_S         0
+
+#define        AR9170_PHY_REG_TIMING9                  (AR9170_PHY_REG_BASE + 0x0198)
+#define        AR9170_PHY_REG_TIMING10                 (AR9170_PHY_REG_BASE + 0x019c)
+#define                AR9170_PHY_TIMING10_PILOT_MASK_2        0x000fffff
+#define                AR9170_PHY_TIMING10_PILOT_MASK_2_S      0
+
+#define        AR9170_PHY_REG_TIMING11                 (AR9170_PHY_REG_BASE + 0x01a0)
+#define                AR9170_PHY_TIMING11_SPUR_DELTA_PHASE    0x000fffff
+#define                AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S  0
+#define                AR9170_PHY_TIMING11_SPUR_FREQ_SD        0x3ff00000
+#define                AR9170_PHY_TIMING11_SPUR_FREQ_SD_S      20
+#define                AR9170_PHY_TIMING11_USE_SPUR_IN_AGC     0x40000000
+#define                AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
+
+#define        AR9170_PHY_REG_RX_CHAINMASK             (AR9170_PHY_REG_BASE + 0x01a4)
+#define        AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \
+                                                0x01b4 + ((_i) << 12))
+#define                AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE             0x40000000
+#define                AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE        0x80000000
+
+#define        AR9170_PHY_REG_MULTICHAIN_GAIN_CTL      (AR9170_PHY_REG_BASE + 0x01ac)
+#define                AR9170_PHY_9285_ANT_DIV_CTL_ALL         0x7f000000
+#define                AR9170_PHY_9285_ANT_DIV_CTL             0x01000000
+#define                AR9170_PHY_9285_ANT_DIV_CTL_S           24
+#define                AR9170_PHY_9285_ANT_DIV_ALT_LNACONF     0x06000000
+#define                AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S   25
+#define                AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF    0x18000000
+#define                AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S  27
+#define                AR9170_PHY_9285_ANT_DIV_ALT_GAINTB      0x20000000
+#define                AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S    29
+#define                AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB     0x40000000
+#define                AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S   30
+#define                AR9170_PHY_9285_ANT_DIV_LNA1            2
+#define                AR9170_PHY_9285_ANT_DIV_LNA2            1
+#define                AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2  3
+#define                AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
+#define                AR9170_PHY_9285_ANT_DIV_GAINTB_0        0
+#define                AR9170_PHY_9285_ANT_DIV_GAINTB_1        1
+
+#define        AR9170_PHY_REG_EXT_CCA0                 (AR9170_PHY_REG_BASE + 0x01b8)
+#define                AR9170_PHY_REG_EXT_CCA0_THRESH62        0x000000ff
+#define                AR9170_PHY_REG_EXT_CCA0_THRESH62_S      0
+
+#define        AR9170_PHY_REG_EXT_CCA                  (AR9170_PHY_REG_BASE + 0x01bc)
+#define                AR9170_PHY_EXT_CCA_CYCPWR_THR1          0x0000fe00
+#define                AR9170_PHY_EXT_CCA_CYCPWR_THR1_S        9
+#define                AR9170_PHY_EXT_CCA_THRESH62             0x007f0000
+#define                AR9170_PHY_EXT_CCA_THRESH62_S           16
+#define                AR9170_PHY_EXT_MINCCA_PWR               0xff800000
+#define                AR9170_PHY_EXT_MINCCA_PWR_S             23
+
+#define        AR9170_PHY_REG_SFCORR_EXT               (AR9170_PHY_REG_BASE + 0x01c0)
+#define                AR9170_PHY_SFCORR_EXT_M1_THRESH         0x0000007f
+#define                AR9170_PHY_SFCORR_EXT_M1_THRESH_S       0
+#define                AR9170_PHY_SFCORR_EXT_M2_THRESH         0x00003f80
+#define                AR9170_PHY_SFCORR_EXT_M2_THRESH_S       7
+#define                AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW     0x001fc000
+#define                AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S   14
+#define                AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW     0x0fe00000
+#define                AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S   21
+#define                AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S     28
+
+#define        AR9170_PHY_REG_HALFGI                   (AR9170_PHY_REG_BASE + 0x01d0)
+#define                AR9170_PHY_HALFGI_DSC_MAN               0x0007fff0
+#define                AR9170_PHY_HALFGI_DSC_MAN_S             4
+#define                AR9170_PHY_HALFGI_DSC_EXP               0x0000000f
+#define                AR9170_PHY_HALFGI_DSC_EXP_S             0
+
+#define        AR9170_PHY_REG_CHANNEL_MASK_01_30       (AR9170_PHY_REG_BASE + 0x01d4)
+#define        AR9170_PHY_REG_CHANNEL_MASK_31_60       (AR9170_PHY_REG_BASE + 0x01d8)
+
+#define        AR9170_PHY_REG_CHAN_INFO_MEMORY         (AR9170_PHY_REG_BASE + 0x01dc)
+#define                AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK        0x0001
+
+#define        AR9170_PHY_REG_HEAVY_CLIP_ENABLE        (AR9170_PHY_REG_BASE + 0x01e0)
+#define        AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS   (AR9170_PHY_REG_BASE + 0x01ec)
+#define                AR9170_PHY_RIFS_INIT_DELAY              0x03ff0000
+
+#define        AR9170_PHY_REG_CALMODE                  (AR9170_PHY_REG_BASE + 0x01f0)
+#define                AR9170_PHY_CALMODE_IQ                   0x00000000
+#define                AR9170_PHY_CALMODE_ADC_GAIN             0x00000001
+#define                AR9170_PHY_CALMODE_ADC_DC_PER           0x00000002
+#define                AR9170_PHY_CALMODE_ADC_DC_INIT          0x00000003
+
+#define        AR9170_PHY_REG_REFCLKDLY                (AR9170_PHY_REG_BASE + 0x01f4)
+#define        AR9170_PHY_REG_REFCLKPD                 (AR9170_PHY_REG_BASE + 0x01f8)
+
+
+#define        AR9170_PHY_REG_CAL_MEAS_0(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0410 + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_1(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0414 \ + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_2(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x0418 + ((_i) << 12))
+#define        AR9170_PHY_REG_CAL_MEAS_3(_i)           (AR9170_PHY_REG_BASE + \
+                                                0x041c + ((_i) << 12))
+
+#define        AR9170_PHY_REG_CURRENT_RSSI             (AR9170_PHY_REG_BASE + 0x041c)
+
+#define        AR9170_PHY_REG_RFBUS_GRANT              (AR9170_PHY_REG_BASE + 0x0420)
+#define                AR9170_PHY_RFBUS_GRANT_EN               0x00000001
+
+#define        AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF      (AR9170_PHY_REG_BASE + 0x04f4)
+#define                AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT      320
+
+#define        AR9170_PHY_REG_CHAN_INFO_GAIN           (AR9170_PHY_REG_BASE + 0x04fc)
+
+#define        AR9170_PHY_REG_MODE                     (AR9170_PHY_REG_BASE + 0x0a00)
+#define                AR9170_PHY_MODE_ASYNCFIFO               0x80
+#define                AR9170_PHY_MODE_AR2133                  0x08
+#define                AR9170_PHY_MODE_AR5111                  0x00
+#define                AR9170_PHY_MODE_AR5112                  0x08
+#define                AR9170_PHY_MODE_DYNAMIC                 0x04
+#define                AR9170_PHY_MODE_RF2GHZ                  0x02
+#define                AR9170_PHY_MODE_RF5GHZ                  0x00
+#define                AR9170_PHY_MODE_CCK                     0x01
+#define                AR9170_PHY_MODE_OFDM                    0x00
+#define                AR9170_PHY_MODE_DYN_CCK_DISABLE         0x100
+
+#define        AR9170_PHY_REG_CCK_TX_CTRL              (AR9170_PHY_REG_BASE + 0x0a04)
+#define                AR9170_PHY_CCK_TX_CTRL_JAPAN                    0x00000010
+#define                AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK         0x0000000c
+#define                AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S       2
+
+#define        AR9170_PHY_REG_CCK_DETECT               (AR9170_PHY_REG_BASE + 0x0a08)
+#define                AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK          0x0000003f
+#define                AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S        0
+/* [12:6] settling time for antenna switch */
+#define                AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME           0x00001fc0
+#define                AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S         6
+#define                AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV    0x2000
+#define                AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S  13
+
+#define        AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2        (AR9170_PHY_REG_BASE + 0x2a0c)
+#define        AR9170_PHY_REG_GAIN_2GHZ                (AR9170_PHY_REG_BASE + 0x0a0c)
+#define                AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN        0x00fc0000
+#define                AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S      18
+#define                AR9170_PHY_GAIN_2GHZ_BSW_MARGIN         0x00003c00
+#define                AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S       10
+#define                AR9170_PHY_GAIN_2GHZ_BSW_ATTEN          0x0000001f
+#define                AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S        0
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN     0x003e0000
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S   17
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN     0x0001f000
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S   12
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN2_DB         0x00000fc0
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S       6
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN1_DB         0x0000003f
+#define                AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S       0
+
+#define        AR9170_PHY_REG_CCK_RXCTRL4              (AR9170_PHY_REG_BASE + 0x0a1c)
+#define                AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT   0x01f80000
+#define                AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
+
+#define        AR9170_PHY_REG_DAG_CTRLCCK              (AR9170_PHY_REG_BASE + 0x0a28)
+#define                AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR      0x00000200
+#define                AR9170_REG_DAG_CTRLCCK_RSSI_THR         0x0001fc00
+#define                AR9170_REG_DAG_CTRLCCK_RSSI_THR_S       10
+
+#define        AR9170_PHY_REG_FORCE_CLKEN_CCK          (AR9170_PHY_REG_BASE + 0x0a2c)
+#define                AR9170_FORCE_CLKEN_CCK_MRC_MUX          0x00000040
+
+#define        AR9170_PHY_REG_POWER_TX_RATE3           (AR9170_PHY_REG_BASE + 0x0a34)
+#define        AR9170_PHY_REG_POWER_TX_RATE4           (AR9170_PHY_REG_BASE + 0x0a38)
+
+#define        AR9170_PHY_REG_SCRM_SEQ_XR              (AR9170_PHY_REG_BASE + 0x0a3c)
+#define        AR9170_PHY_REG_HEADER_DETECT_XR         (AR9170_PHY_REG_BASE + 0x0a40)
+#define        AR9170_PHY_REG_CHIRP_DETECTED_XR        (AR9170_PHY_REG_BASE + 0x0a44)
+#define        AR9170_PHY_REG_BLUETOOTH                (AR9170_PHY_REG_BASE + 0x0a54)
+
+#define        AR9170_PHY_REG_TPCRG1                   (AR9170_PHY_REG_BASE + 0x0a58)
+#define                AR9170_PHY_TPCRG1_NUM_PD_GAIN           0x0000c000
+#define                AR9170_PHY_TPCRG1_NUM_PD_GAIN_S         14
+#define                AR9170_PHY_TPCRG1_PD_GAIN_1             0x00030000
+#define                AR9170_PHY_TPCRG1_PD_GAIN_1_S           16
+#define                AR9170_PHY_TPCRG1_PD_GAIN_2             0x000c0000
+#define                AR9170_PHY_TPCRG1_PD_GAIN_2_S           18
+#define                AR9170_PHY_TPCRG1_PD_GAIN_3             0x00300000
+#define                AR9170_PHY_TPCRG1_PD_GAIN_3_S           20
+#define                AR9170_PHY_TPCRG1_PD_CAL_ENABLE         0x00400000
+#define                AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S       22
+
+#define        AR9170_PHY_REG_TX_PWRCTRL4              (AR9170_PHY_REG_BASE + 0x0a64)
+#define                AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID      0x00000001
+#define                AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S    0
+#define                AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT        0x000001fe
+#define                AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S      1
+
+#define        AR9170_PHY_REG_ANALOG_SWAP              (AR9170_PHY_REG_BASE + 0x0a68)
+#define                AR9170_PHY_ANALOG_SWAP_AB               0x0001
+#define                AR9170_PHY_ANALOG_SWAP_ALT_CHAIN        0x00000040
+
+#define        AR9170_PHY_REG_TPCRG5                   (AR9170_PHY_REG_BASE + 0x0a6c)
+#define                AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP       0x0000000f
+#define                AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S     0
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1    0x000003f0
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S  4
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2    0x0000fc00
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S  10
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3    0x003f0000
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S  16
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4    0x0fc00000
+#define                AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S  22
+
+#define        AR9170_PHY_REG_TX_PWRCTRL6_0            (AR9170_PHY_REG_BASE + 0x0a70)
+#define        AR9170_PHY_REG_TX_PWRCTRL6_1            (AR9170_PHY_REG_BASE + 0x1a70)
+#define                AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE      0x03000000
+#define                AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S    24
+
+#define        AR9170_PHY_REG_TX_PWRCTRL7              (AR9170_PHY_REG_BASE + 0x0a74)
+#define                AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN      0x01f80000
+#define                AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S    19
+
+#define        AR9170_PHY_REG_TX_PWRCTRL9              (AR9170_PHY_REG_BASE + 0x0a7c)
+#define                AR9170_PHY_TX_DESIRED_SCALE_CCK         0x00007c00
+#define                AR9170_PHY_TX_DESIRED_SCALE_CCK_S       10
+#define                AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL   0x80000000
+#define                AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
+
+#define        AR9170_PHY_REG_TX_GAIN_TBL1             (AR9170_PHY_REG_BASE + 0x0b00)
+#define                AR9170_PHY_TX_GAIN                      0x0007f000
+#define                AR9170_PHY_TX_GAIN_S                    12
+
+/* Carrier leak calibration control, do it after AGC calibration */
+#define        AR9170_PHY_REG_CL_CAL_CTL               (AR9170_PHY_REG_BASE + 0x0b58)
+#define                AR9170_PHY_CL_CAL_ENABLE                0x00000002
+#define                AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE   0x00000001
+
+#define        AR9170_PHY_REG_POWER_TX_RATE5           (AR9170_PHY_REG_BASE + 0x0b8c)
+#define        AR9170_PHY_REG_POWER_TX_RATE6           (AR9170_PHY_REG_BASE + 0x0b90)
+
+#define        AR9170_PHY_REG_CH0_TX_PWRCTRL11         (AR9170_PHY_REG_BASE + 0x0b98)
+#define        AR9170_PHY_REG_CH1_TX_PWRCTRL11         (AR9170_PHY_REG_BASE + 0x1b98)
+#define                AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP        0x0000fc00
+#define                AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S      10
+
+#define        AR9170_PHY_REG_CAL_CHAINMASK            (AR9170_PHY_REG_BASE + 0x0b9c)
+#define        AR9170_PHY_REG_VIT_MASK2_M_46_61        (AR9170_PHY_REG_BASE + 0x0ba0)
+#define        AR9170_PHY_REG_MASK2_M_31_45            (AR9170_PHY_REG_BASE + 0x0ba4)
+#define        AR9170_PHY_REG_MASK2_M_16_30            (AR9170_PHY_REG_BASE + 0x0ba8)
+#define        AR9170_PHY_REG_MASK2_M_00_15            (AR9170_PHY_REG_BASE + 0x0bac)
+#define        AR9170_PHY_REG_PILOT_MASK_01_30         (AR9170_PHY_REG_BASE + 0x0bb0)
+#define        AR9170_PHY_REG_PILOT_MASK_31_60         (AR9170_PHY_REG_BASE + 0x0bb4)
+#define        AR9170_PHY_REG_MASK2_P_15_01            (AR9170_PHY_REG_BASE + 0x0bb8)
+#define        AR9170_PHY_REG_MASK2_P_30_16            (AR9170_PHY_REG_BASE + 0x0bbc)
+#define        AR9170_PHY_REG_MASK2_P_45_31            (AR9170_PHY_REG_BASE + 0x0bc0)
+#define        AR9170_PHY_REG_MASK2_P_61_45            (AR9170_PHY_REG_BASE + 0x0bc4)
+#define        AR9170_PHY_REG_POWER_TX_SUB             (AR9170_PHY_REG_BASE + 0x0bc8)
+#define        AR9170_PHY_REG_POWER_TX_RATE7           (AR9170_PHY_REG_BASE + 0x0bcc)
+#define        AR9170_PHY_REG_POWER_TX_RATE8           (AR9170_PHY_REG_BASE + 0x0bd0)
+#define        AR9170_PHY_REG_POWER_TX_RATE9           (AR9170_PHY_REG_BASE + 0x0bd4)
+#define        AR9170_PHY_REG_XPA_CFG                  (AR9170_PHY_REG_BASE + 0x0bd8)
+#define                AR9170_PHY_FORCE_XPA_CFG                0x000000001
+#define                AR9170_PHY_FORCE_XPA_CFG_S              0
+
+#define        AR9170_PHY_REG_CH1_CCA                  (AR9170_PHY_REG_BASE + 0x1064)
+#define                AR9170_PHY_CH1_MINCCA_PWR               0x0ff80000
+#define                AR9170_PHY_CH1_MINCCA_PWR_S             19
+
+#define        AR9170_PHY_REG_CH2_CCA                  (AR9170_PHY_REG_BASE + 0x2064)
+#define                AR9170_PHY_CH2_MINCCA_PWR               0x0ff80000
+#define                AR9170_PHY_CH2_MINCCA_PWR_S             19
+
+#define        AR9170_PHY_REG_CH1_EXT_CCA              (AR9170_PHY_REG_BASE + 0x11bc)
+#define                AR9170_PHY_CH1_EXT_MINCCA_PWR           0xff800000
+#define                AR9170_PHY_CH1_EXT_MINCCA_PWR_S         23
+
+#define        AR9170_PHY_REG_CH2_EXT_CCA              (AR9170_PHY_REG_BASE + 0x21bc)
+#define                AR9170_PHY_CH2_EXT_MINCCA_PWR           0xff800000
+#define                AR9170_PHY_CH2_EXT_MINCCA_PWR_S         23
+
+#define        REDUCE_CHAIN_0 0x00000050
+#define        REDUCE_CHAIN_1 0x00000051
+
+#endif /* __CARL9170_SHARED_PHY_H */
diff --git a/drivers/net/wireless/ath/carl9170/wlan.h b/drivers/net/wireless/ath/carl9170/wlan.h
new file mode 100644 (file)
index 0000000..48ead22
--- /dev/null
@@ -0,0 +1,412 @@
+/*
+ * Shared Atheros AR9170 Header
+ *
+ * RX/TX meta descriptor format
+ *
+ * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, see
+ * http://www.gnu.org/licenses/.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *    Copyright (c) 2007-2008 Atheros Communications, Inc.
+ *
+ *    Permission to use, copy, modify, and/or distribute this software for any
+ *    purpose with or without fee is hereby granted, provided that the above
+ *    copyright notice and this permission notice appear in all copies.
+ *
+ *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __CARL9170_SHARED_WLAN_H
+#define __CARL9170_SHARED_WLAN_H
+
+#include "fwcmd.h"
+
+#define        AR9170_RX_PHY_RATE_CCK_1M               0x0a
+#define        AR9170_RX_PHY_RATE_CCK_2M               0x14
+#define        AR9170_RX_PHY_RATE_CCK_5M               0x37
+#define        AR9170_RX_PHY_RATE_CCK_11M              0x6e
+
+#define        AR9170_ENC_ALG_NONE                     0x0
+#define        AR9170_ENC_ALG_WEP64                    0x1
+#define        AR9170_ENC_ALG_TKIP                     0x2
+#define        AR9170_ENC_ALG_AESCCMP                  0x4
+#define        AR9170_ENC_ALG_WEP128                   0x5
+#define        AR9170_ENC_ALG_WEP256                   0x6
+#define        AR9170_ENC_ALG_CENC                     0x7
+
+#define        AR9170_RX_ENC_SOFTWARE                  0x8
+
+#define        AR9170_RX_STATUS_MODULATION             0x03
+#define        AR9170_RX_STATUS_MODULATION_S           0
+#define        AR9170_RX_STATUS_MODULATION_CCK         0x00
+#define        AR9170_RX_STATUS_MODULATION_OFDM        0x01
+#define        AR9170_RX_STATUS_MODULATION_HT          0x02
+#define        AR9170_RX_STATUS_MODULATION_DUPOFDM     0x03
+
+/* depends on modulation */
+#define        AR9170_RX_STATUS_SHORT_PREAMBLE         0x08
+#define        AR9170_RX_STATUS_GREENFIELD             0x08
+
+#define        AR9170_RX_STATUS_MPDU                   0x30
+#define        AR9170_RX_STATUS_MPDU_S                 4
+#define        AR9170_RX_STATUS_MPDU_SINGLE            0x00
+#define        AR9170_RX_STATUS_MPDU_FIRST             0x20
+#define        AR9170_RX_STATUS_MPDU_MIDDLE            0x30
+#define        AR9170_RX_STATUS_MPDU_LAST              0x10
+
+#define        AR9170_RX_ERROR_RXTO                    0x01
+#define        AR9170_RX_ERROR_OVERRUN                 0x02
+#define        AR9170_RX_ERROR_DECRYPT                 0x04
+#define        AR9170_RX_ERROR_FCS                     0x08
+#define        AR9170_RX_ERROR_WRONG_RA                0x10
+#define        AR9170_RX_ERROR_PLCP                    0x20
+#define        AR9170_RX_ERROR_MMIC                    0x40
+#define        AR9170_RX_ERROR_FATAL                   0x80
+
+/* these are either-or */
+#define        AR9170_TX_MAC_PROT_RTS                  0x0001
+#define        AR9170_TX_MAC_PROT_CTS                  0x0002
+#define        AR9170_TX_MAC_PROT                      0x0003
+
+#define        AR9170_TX_MAC_NO_ACK                    0x0004
+/* if unset, MAC will only do SIFS space before frame */
+#define        AR9170_TX_MAC_BACKOFF                   0x0008
+#define        AR9170_TX_MAC_BURST                     0x0010
+#define        AR9170_TX_MAC_AGGR                      0x0020
+
+/* encryption is a two-bit field */
+#define        AR9170_TX_MAC_ENCR_NONE                 0x0000
+#define        AR9170_TX_MAC_ENCR_RC4                  0x0040
+#define        AR9170_TX_MAC_ENCR_CENC                 0x0080
+#define        AR9170_TX_MAC_ENCR_AES                  0x00c0
+
+#define        AR9170_TX_MAC_MMIC                      0x0100
+#define        AR9170_TX_MAC_HW_DURATION               0x0200
+#define        AR9170_TX_MAC_QOS_S                     10
+#define        AR9170_TX_MAC_QOS                       0x0c00
+#define        AR9170_TX_MAC_DISABLE_TXOP              0x1000
+#define        AR9170_TX_MAC_TXOP_RIFS                 0x2000
+#define        AR9170_TX_MAC_IMM_BA                    0x4000
+
+/* either-or */
+#define        AR9170_TX_PHY_MOD_CCK                   0x00000000
+#define        AR9170_TX_PHY_MOD_OFDM                  0x00000001
+#define        AR9170_TX_PHY_MOD_HT                    0x00000002
+
+/* depends on modulation */
+#define        AR9170_TX_PHY_SHORT_PREAMBLE            0x00000004
+#define        AR9170_TX_PHY_GREENFIELD                0x00000004
+
+#define        AR9170_TX_PHY_BW_S                      3
+#define        AR9170_TX_PHY_BW                        (3 << AR9170_TX_PHY_BW_SHIFT)
+#define        AR9170_TX_PHY_BW_20MHZ                  0
+#define        AR9170_TX_PHY_BW_40MHZ                  2
+#define        AR9170_TX_PHY_BW_40MHZ_DUP              3
+
+#define        AR9170_TX_PHY_TX_HEAVY_CLIP_S           6
+#define        AR9170_TX_PHY_TX_HEAVY_CLIP             (7 << \
+                                                AR9170_TX_PHY_TX_HEAVY_CLIP_S)
+
+#define        AR9170_TX_PHY_TX_PWR_S                  9
+#define        AR9170_TX_PHY_TX_PWR                    (0x3f << \
+                                                AR9170_TX_PHY_TX_PWR_S)
+
+#define        AR9170_TX_PHY_TXCHAIN_S                 15
+#define        AR9170_TX_PHY_TXCHAIN                   (7 << \
+                                                AR9170_TX_PHY_TXCHAIN_S)
+#define        AR9170_TX_PHY_TXCHAIN_1                 1
+/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
+#define        AR9170_TX_PHY_TXCHAIN_2                 5
+
+#define        AR9170_TX_PHY_MCS_S                     18
+#define        AR9170_TX_PHY_MCS                       (0x7f << \
+                                                AR9170_TX_PHY_MCS_S)
+
+#define        AR9170_TX_PHY_RATE_CCK_1M               0x0
+#define        AR9170_TX_PHY_RATE_CCK_2M               0x1
+#define        AR9170_TX_PHY_RATE_CCK_5M               0x2
+#define        AR9170_TX_PHY_RATE_CCK_11M              0x3
+
+/* same as AR9170_RX_PHY_RATE */
+#define        AR9170_TXRX_PHY_RATE_OFDM_6M            0xb
+#define        AR9170_TXRX_PHY_RATE_OFDM_9M            0xf
+#define        AR9170_TXRX_PHY_RATE_OFDM_12M           0xa
+#define        AR9170_TXRX_PHY_RATE_OFDM_18M           0xe
+#define        AR9170_TXRX_PHY_RATE_OFDM_24M           0x9
+#define        AR9170_TXRX_PHY_RATE_OFDM_36M           0xd
+#define        AR9170_TXRX_PHY_RATE_OFDM_48M           0x8
+#define        AR9170_TXRX_PHY_RATE_OFDM_54M           0xc
+
+#define        AR9170_TXRX_PHY_RATE_HT_MCS0            0x0
+#define        AR9170_TXRX_PHY_RATE_HT_MCS1            0x1
+#define        AR9170_TXRX_PHY_RATE_HT_MCS2            0x2
+#define        AR9170_TXRX_PHY_RATE_HT_MCS3            0x3
+#define        AR9170_TXRX_PHY_RATE_HT_MCS4            0x4
+#define        AR9170_TXRX_PHY_RATE_HT_MCS5            0x5
+#define        AR9170_TXRX_PHY_RATE_HT_MCS6            0x6
+#define        AR9170_TXRX_PHY_RATE_HT_MCS7            0x7
+#define        AR9170_TXRX_PHY_RATE_HT_MCS8            0x8
+#define        AR9170_TXRX_PHY_RATE_HT_MCS9            0x9
+#define        AR9170_TXRX_PHY_RATE_HT_MCS10           0xa
+#define        AR9170_TXRX_PHY_RATE_HT_MCS11           0xb
+#define        AR9170_TXRX_PHY_RATE_HT_MCS12           0xc
+#define        AR9170_TXRX_PHY_RATE_HT_MCS13           0xd
+#define        AR9170_TXRX_PHY_RATE_HT_MCS14           0xe
+#define        AR9170_TXRX_PHY_RATE_HT_MCS15           0xf
+
+#define        AR9170_TX_PHY_SHORT_GI                  0x80000000
+
+#ifdef __CARL9170FW__
+struct ar9170_tx_hw_mac_control {
+       union {
+               struct {
+                       /*
+                        * Beware of compiler bugs in all gcc pre 4.4!
+                        */
+
+                       u8 erp_prot:2;
+                       u8 no_ack:1;
+                       u8 backoff:1;
+                       u8 burst:1;
+                       u8 ampdu:1;
+
+                       u8 enc_mode:2;
+
+                       u8 hw_mmic:1;
+                       u8 hw_duration:1;
+
+                       u8 qos_queue:2;
+
+                       u8 disable_txop:1;
+                       u8 txop_rifs:1;
+
+                       u8 ba_end:1;
+                       u8 probe:1;
+               } __packed;
+
+               __le16 set;
+       } __packed;
+} __packed;
+
+struct ar9170_tx_hw_phy_control {
+       union {
+               struct {
+                       /*
+                        * Beware of compiler bugs in all gcc pre 4.4!
+                        */
+
+                       u8 modulation:2;
+                       u8 preamble:1;
+                       u8 bandwidth:2;
+                       u8:1;
+                       u8 heavy_clip:3;
+                       u8 tx_power:6;
+                       u8 chains:3;
+                       u8 mcs:7;
+                       u8:6;
+                       u8 short_gi:1;
+               } __packed;
+
+               __le32 set;
+       } __packed;
+} __packed;
+
+struct ar9170_tx_rate_info {
+       u8 tries:3;
+       u8 erp_prot:2;
+       u8 ampdu:1;
+       u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
+} __packed;
+
+struct carl9170_tx_superdesc {
+       __le16 len;
+       u8 rix;
+       u8 cnt;
+       u8 cookie;
+       u8 ampdu_density:3;
+       u8 ampdu_factor:2;
+       u8 ampdu_commit_density:1;
+       u8 ampdu_commit_factor:1;
+       u8 ampdu_unused_bit:1;
+       u8 queue:2;
+       u8 reserved:1;
+       u8 vif_id:3;
+       u8 fill_in_tsf:1;
+       u8 cab:1;
+       u8 padding2;
+       struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
+       struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
+} __packed;
+
+struct ar9170_tx_hwdesc {
+       __le16 length;
+       struct ar9170_tx_hw_mac_control mac;
+       struct ar9170_tx_hw_phy_control phy;
+} __packed;
+
+struct ar9170_tx_frame {
+       struct ar9170_tx_hwdesc hdr;
+
+       union {
+               struct ieee80211_hdr i3e;
+               u8 payload[0];
+       } data;
+} __packed;
+
+struct carl9170_tx_superframe {
+       struct carl9170_tx_superdesc s;
+       struct ar9170_tx_frame f;
+} __packed;
+
+#endif /* __CARL9170FW__ */
+
+struct _ar9170_tx_hwdesc {
+       __le16 length;
+       __le16 mac_control;
+       __le32 phy_control;
+} __packed;
+
+#define        CARL9170_TX_SUPER_AMPDU_DENSITY_S               0
+#define        CARL9170_TX_SUPER_AMPDU_DENSITY                 0x7
+#define        CARL9170_TX_SUPER_AMPDU_FACTOR                  0x18
+#define        CARL9170_TX_SUPER_AMPDU_FACTOR_S                3
+#define        CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY          0x20
+#define        CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S        5
+#define        CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR           0x40
+#define        CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S         6
+
+#define CARL9170_TX_SUPER_MISC_QUEUE                   0x3
+#define CARL9170_TX_SUPER_MISC_QUEUE_S                 0
+#define        CARL9170_TX_SUPER_MISC_VIF_ID                   0x38
+#define        CARL9170_TX_SUPER_MISC_VIF_ID_S                 3
+#define        CARL9170_TX_SUPER_MISC_FILL_IN_TSF              0x40
+#define        CARL9170_TX_SUPER_MISC_CAB                      0x80
+
+#define CARL9170_TX_SUPER_RI_TRIES                     0x7
+#define CARL9170_TX_SUPER_RI_TRIES_S                   0
+#define CARL9170_TX_SUPER_RI_ERP_PROT                  0x18
+#define CARL9170_TX_SUPER_RI_ERP_PROT_S                        3
+#define CARL9170_TX_SUPER_RI_AMPDU                     0x20
+#define CARL9170_TX_SUPER_RI_AMPDU_S                   5
+
+struct _carl9170_tx_superdesc {
+       __le16 len;
+       u8 rix;
+       u8 cnt;
+       u8 cookie;
+       u8 ampdu_settings;
+       u8 misc;
+       u8 padding;
+       u8 ri[CARL9170_TX_MAX_RATES];
+       __le32 rr[CARL9170_TX_MAX_RETRY_RATES];
+} __packed;
+
+struct _carl9170_tx_superframe {
+       struct _carl9170_tx_superdesc s;
+       struct _ar9170_tx_hwdesc f;
+       u8 frame_data[0];
+} __packed;
+
+#define        CARL9170_TX_SUPERDESC_LEN               24
+#define        AR9170_TX_HWDESC_LEN                    8
+#define        AR9170_TX_SUPERFRAME_LEN                (CARL9170_TX_HWDESC_LEN + \
+                                                AR9170_TX_SUPERDESC_LEN)
+
+struct ar9170_rx_head {
+       u8 plcp[12];
+} __packed;
+
+struct ar9170_rx_phystatus {
+       union {
+               struct {
+                       u8 rssi_ant0, rssi_ant1, rssi_ant2,
+                               rssi_ant0x, rssi_ant1x, rssi_ant2x,
+                               rssi_combined;
+               } __packed;
+               u8 rssi[7];
+       } __packed;
+
+       u8 evm_stream0[6], evm_stream1[6];
+       u8 phy_err;
+} __packed;
+
+struct ar9170_rx_macstatus {
+       u8 SAidx, DAidx;
+       u8 error;
+       u8 status;
+} __packed;
+
+struct ar9170_rx_frame_single {
+       struct ar9170_rx_head phy_head;
+       struct ieee80211_hdr i3e;
+       struct ar9170_rx_phystatus phy_tail;
+       struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_head {
+       struct ar9170_rx_head phy_head;
+       struct ieee80211_hdr i3e;
+       struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_middle {
+       struct ieee80211_hdr i3e;
+       struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame_tail {
+       struct ieee80211_hdr i3e;
+       struct ar9170_rx_phystatus phy_tail;
+       struct ar9170_rx_macstatus macstatus;
+} __packed;
+
+struct ar9170_rx_frame {
+       union {
+               struct ar9170_rx_frame_single single;
+               struct ar9170_rx_frame_head head;
+               struct ar9170_rx_frame_middle middle;
+               struct ar9170_rx_frame_tail tail;
+       } __packed;
+} __packed;
+
+static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
+{
+       return (t->SAidx & 0xc0) >> 4 |
+              (t->DAidx & 0xc0) >> 6;
+}
+
+enum ar9170_txq {
+       AR9170_TXQ_BE,
+
+       AR9170_TXQ_VI,
+       AR9170_TXQ_VO,
+       AR9170_TXQ_BK,
+
+       __AR9170_NUM_TXQ,
+};
+
+static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 };
+
+#define        AR9170_TXQ_DEPTH                        32
+
+#endif /* __CARL9170_SHARED_WLAN_H */