riscv: deconfig: Enable the riscv cpuidle config

Signed-off-by: mason.huo <mason.huo@starfivetech.com>

diff --git a/arch/riscv/configs/starfive_jh7110_defconfig b/arch/riscv/configs/starfive_jh7110_defconfig
index 88a1cac..cda0d41 100644 (file)
--- a/arch/riscv/configs/starfive_jh7110_defconfig
+++ b/arch/riscv/configs/starfive_jh7110_defconfig
@@ -22,6 +22,7 @@ CONFIG_SMP=y
 CONFIG_HZ_100=y
 CONFIG_PM=y
 CONFIG_CPU_IDLE=y
+CONFIG_RISCV_SBI_CPUIDLE=y
 # CONFIG_SECCOMP is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y