*.asn1.[ch]
*.bin
*.cfgout
+*.cover
*.dtb
*.dtbo
*.dtb.S
*.lex.c
*.lst
*.mod.c
+*.mbx
*.o
*.o.*
*.order
* off: FFF
*/
-u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
+static int get_effective_el(void)
{
+ int el = current_el();
+
+ if (el == 2) {
+ u64 hcr_el2;
+
+ /*
+ * If we are using the EL2&0 translation regime, the TCR_EL2
+ * looks like the EL1 version, even though we are in EL2.
+ */
+ __asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
+ if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
+ return 1;
+ }
+
+ return el;
+}
+
+u64 get_tcr(u64 *pips, u64 *pva_bits)
+{
+ int el = get_effective_el();
u64 max_addr = 0;
u64 ips, va_bits;
u64 tcr;
debug("addr=%llx level=%d\n", addr, level);
- get_tcr(0, NULL, &va_bits);
+ get_tcr(NULL, &va_bits);
if (va_bits < 39)
start_level = 1;
u64 va_bits;
int start_level = 0;
- get_tcr(0, NULL, &va_bits);
+ get_tcr(NULL, &va_bits);
if (va_bits < 39)
start_level = 1;
setup_all_pgtables();
el = current_el();
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
/* enable the mmu */
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- get_tcr(el, NULL, NULL) &
+ get_tcr(NULL, NULL) &
~(TCR_ORGN_MASK | TCR_IRGN_MASK),
MEMORY_ATTRIBUTES);
invalidate_icache_all();
/* point TTBR to the new table */
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
MEMORY_ATTRIBUTES);
set_sctlr(get_sctlr() | CR_M);
msr cptr_el3, xzr /* Enable FP/SIMD */
b 0f
2: mrs x1, hcr_el2
- tbnz x1, #34, 1f /* HCR_EL2.E2H */
+ tbnz x1, #HCR_EL2_E2H_BIT, 1f /* HCR_EL2.E2H */
orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */
msr hcr_el2, x1
set_vbar vbar_el2, x0
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&uart1 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&uart2 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&uart3 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
/*
* U-Boot additions
*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_agilex-u-boot.dtsi"
aliases {
spi0 = &qspi;
i2c0 = &i2c1;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@f9000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0xf9000450 0x00000010>;
+ status = "disabled";
+ };
};
memory {
/*
* U-Boot additions
*
- * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*/
#include "socfpga_stratix10-u-boot.dtsi"
/{
aliases {
spi0 = &qspi;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@f9000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0xf9000450 0x00000010>;
+ status = "disabled";
+ };
};
};
broken-cd;
bus-width = <4>;
drvsel = <3>;
- smplsel = <0>;
+ smplsel = <2>;
};
&qspi {
#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
#define TCR_EL3_RSVD (1U << 31 | 1 << 23)
+#define HCR_EL2_E2H_BIT 34
+
#ifndef __ASSEMBLY__
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
extern struct mm_region *mem_map;
void setup_pgtables(void);
-u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
+u64 get_tcr(u64 *pips, u64 *pva_bits);
#endif
#endif /* _ASM_ARMV8_MMU_H_ */
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_PADCFG_MMR1 module registers */
+ mmr_unlock(MCU_PADCFG_MMR1_BASE, 1);
}
/*
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2022 Intel Corporation <www.intel.com>
*
*/
#include <common.h>
#include <init.h>
+#include <div64.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
#endif
return 0;
}
+
+__always_inline u64 __get_time_stamp(void)
+{
+ u64 cntpct;
+
+ isb();
+ asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+
+ return cntpct;
+}
+
+__always_inline uint64_t __usec_to_tick(unsigned long usec)
+{
+ u64 tick = usec;
+ u64 cntfrq;
+
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+ tick *= cntfrq;
+ do_div(tick, 1000000);
+
+ return tick;
+}
+
+__always_inline void __udelay(unsigned long usec)
+{
+ /* get current timestamp */
+ u64 tmp = __get_time_stamp() + __usec_to_tick(usec);
+
+ while (__get_time_stamp() < tmp + 1) /* loop till event */
+ ;
+}
\ No newline at end of file
-BOARDS from CS Systemes d'Information
-M: Christophe Leroy <christophe.leroy@c-s.fr>
+BOARDS from CS GROUP France
+M: Christophe Leroy <christophe.leroy@csgroup.eu>
S: Maintained
F: board/cssi/
F: include/configs/MCR3000.h
#endif
/* CPSW plat */
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL)
struct cpsw_slave_data slave_data[] = {
{
.slave_reg_ofs = CPSW_SLAVE0_OFFSET,
alias powerpc uboot, afleming, stroese, wd, priyankajain, mariosix
alias ppc powerpc
-alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
+alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@csgroup.eu>
alias mpc83xx uboot, mariosix
alias mpc85xx uboot, afleming, priyankajain
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
*
*/
#include <dm.h>
hang();
}
- /* Enable snoop filter, a bit per snoop filter */
- setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+ /* Disable snoop filter, a bit per snoop filter */
+ clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
BIT(f));
}
}
uint32_t *desc;
unsigned int size;
- if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
- !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
- puts("Error: Address arguments are not aligned\n");
- return -EINVAL;
- }
-
desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
if (!desc) {
debug("Not enough memory for descriptor allocation\n");
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
- * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
*
*/
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
*
*/
DDR_SCH_DEVTODEV);
/* assigning the SDRAM size */
- unsigned long long size = sdram_calculate_size(plat);
+ phys_size_t size = sdram_calculate_size(plat);
/* If the size is invalid, use default Config size */
if (size <= 0)
hw_size = PHYS_SDRAM_1_SIZE;
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
*
*/
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
- phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ phys_size_t size = (phys_size_t)1 <<
+ (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
+#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f
#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
err = 0;
ret = clk_get_bulk(dev, &priv->clocks);
- if (ret) {
+ if (ret && ret != -ENOENT) {
dev_err(dev, "Failed to get clocks (ret=%d)\n", ret);
return ret;
}
}
err = reset_get_bulk(dev, &priv->resets);
- if (err) {
+ if (ret && ret != -ENOENT) {
dev_err(dev, "Failed to get resets (err=%d)\n", err);
goto clk_err;
}
int i_number, offset = 0, ret;
struct fs_dirent *dent;
unsigned char *ipos;
+ u16 name_size;
dirs = (struct squashfs_dir_stream *)fs_dirs;
if (!dirs->size) {
return -SQFS_STOP_READDIR;
}
- /* Set entry name */
- strncpy(dent->name, dirs->entry->name, dirs->entry->name_size + 1);
- dent->name[dirs->entry->name_size + 1] = '\0';
+ /* Set entry name (capped at FS_DIRENT_NAME_LEN which is a U-Boot limitation) */
+ name_size = min_t(u16, dirs->entry->name_size + 1, FS_DIRENT_NAME_LEN - 1);
+ strncpy(dent->name, dirs->entry->name, name_size);
+ dent->name[name_size] = '\0';
offset = dirs->entry->name_size + 1 + SQFS_ENTRY_BASE_LENGTH;
dirs->entry_count--;
"rootfstype=ext4\0" \
"console=console=ttySAC2,115200n8\0" \
"fdtfile=exynos5422-odroidxu3.dtb\0" \
+ "board=odroid\0" \
"board_name=odroidxu3\0" \
"mmcbootdev=0\0" \
"mmcrootdev=0\0" \
"addargs=run addcons addmtd addmisc\0" \
"ubiload=" \
"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \
- "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
+ "ubifsload ${kernel_addr_r} /boot/${bootfile} ; " \
+ "ubifsumount ; ubi detach\0" \
"netload=" \
"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
"miscargs=nohlt panic=1\0" \
#define FS_DT_REG 8 /* regular file */
#define FS_DT_LNK 10 /* symbolic link */
+#define FS_DIRENT_NAME_LEN 256
+
/**
* struct fs_dirent - directory entry
*
/** change_time: time of last modification */
struct rtc_time change_time;
/** name: file name */
- char name[256];
+ char name[FS_DIRENT_NAME_LEN];
};
/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */
default y if SANDBOX
help
Enable this to verify the checksum on UDP packets. If the checksum
- is wrong then the packet is discussed and an error is shown, like
+ is wrong then the packet is discarded and an error is shown, like
"UDP wrong checksum 29374a23 30ff3826"
config BOOTP_SERVERIP
version='1.0',
license='GPL-2.0+',
scripts=['binman'],
- packages=['binman', 'binman.etype'],
+ packages=['binman', 'binman.etype', 'binman.btool'],
package_dir={'binman': ''},
package_data={'binman': ['README.rst', 'entries.rst']},
classifiers=['Environment :: Console',
projects / platform / kernel / u-boot.git / commitdiff