arm64: dts: imx8mn: add crypto node

Add node for CAAM - Cryptographic Acceleration and Assurance Module.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index cce65b9..c3fec19 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -537,6 +537,36 @@
                                status = "disabled";
                        };
 
+                       crypto: crypto@30900000 {
+                               compatible = "fsl,sec-v4.0";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x30900000 0x40000>;
+                               ranges = <0 0x30900000 0x40000>;
+                               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_AHB>,
+                                        <&clk IMX8MN_CLK_IPG_ROOT>;
+                               clock-names = "aclk", "ipg";
+
+                               sec_jr0: jr0@1000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x1000 0x1000>;
+                                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr1: jr1@2000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x2000 0x1000>;
+                                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr2: jr2@3000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x3000 0x1000>;
+                                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+
                        i2c1: i2c@30a20000 {
                                compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
                                #address-cells = <1>;