[RegBankSelect] Reuse RegisterBankInfo logic to get to the register bank

from a register.
On top of duplicating the logic, it was buggy! It would assert on
physical registers, since MachineRegisterInfo does not have any
information regarding register classes/banks for them.

llvm-svn: 265727

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index 57137ec..a7e0b15 100644 (file)
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -71,6 +71,7 @@
 namespace llvm {
 // Forward declarations.
 class MachineRegisterInfo;
+class TargetRegisterInfo;
 
 /// This pass implements the reg bank selector pass used in the GlobalISel
 /// pipeline. At the end of this pass, all register operands have been assigned
@@ -87,6 +88,9 @@ private:
   /// pass uses and updates.
   MachineRegisterInfo *MRI;
 
+  /// Information on the register classes for the current function.
+  const TargetRegisterInfo *TRI;
+
   /// Helper class used for every code morphing.
   MachineIRBuilder MIRBuilder;
 

diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index b417923..4e0650e 100644 (file)
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -33,6 +33,7 @@ void RegBankSelect::init(MachineFunction &MF) {
   RBI = MF.getSubtarget().getRegBankInfo();
   assert(RBI && "Cannot work without RegisterBankInfo");
   MRI = &MF.getRegInfo();
+  TRI = MF.getSubtarget().getRegisterInfo();
   MIRBuilder.setMF(MF);
 }
 
@@ -43,18 +44,7 @@ bool RegBankSelect::assignmentMatch(
   if (ValMapping.BreakDown.size() > 1)
     return false;
 
-  const RegClassOrRegBank &CurAssignment = MRI->getRegClassOrRegBank(Reg);
-  // Nothing assigned, the assignment does not match.
-  if (!CurAssignment)
-    return false;
-  // Get the register bank form the current assignment.
-  const RegisterBank *CurRegBank = nullptr;
-  if (CurAssignment.is<const TargetRegisterClass *>())
-    CurRegBank = &RBI->getRegBankFromRegClass(
-        *CurAssignment.get<const TargetRegisterClass *>());
-  else
-    CurRegBank = CurAssignment.get<const RegisterBank *>();
-  return CurRegBank == ValMapping.BreakDown[0].RegBank;
+  return RBI->getRegBank(Reg, *MRI, *TRI) == ValMapping.BreakDown[0].RegBank;
 }
 
 unsigned